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this is information on a product in full production. august 2012 doc id 15457 rev 8 1/160 1 spc56el60x, spc56el54x spc564l60x, spc564l54x 32-bit power architecture? microcontroller for automotive sil3/asild chassis an d safety applications datasheet ? production data features high-performance e200z4d dual core ? 32-bit power architecture ? technology cpu ? core frequency as high as 120 mhz ? dual issue five-stage pipeline core ? variable length encoding (vle) ? memory management unit (mmu) ? 4 kb instruction cache with error detection code ? signal processing engine (spe) memory available ? up to 1 mb flash memory with ecc ? up to 128 kb on-chip sram with ecc ? built-in rww capabilities for eeprom emulation sil3/asild innovative safety concept: lockstep mode and fail-safe protection ? sphere of replication (sor) for key components (such as cpu core, edma, crossbar switch) ? fault collection and control unit (fccu) ? redundancy control and checker unit (rccu) on outputs of the sor connected to fccu ? boot-time built-in self-test for memory (mbist) and logic (lbist) triggered by hardware ? boot-time built-in self-test for adc and flash memory triggered by software ? replicated safety enhanced watchdog ? replicated junction temperature sensor ? non-maskable interrupt (nmi) ? 16-region memory protection unit (mpu) ? clock monitoring units (cmu) ? power management unit (pmu) ? cyclic redundancy check (crc) unit decoupled parallel mode for high-performance use of replicated cores nexus class 3+ interface interrupts ? replicated 16-priority controller ? replicated 16-channel edma controller gpios individually programmable as input, output or special function three 6-channel general-purpose etimer units 2 flexpwm units ? four 16-bit channels per module communications interfaces ? 2 linflexd channels ? 3 dspi channels with automatic chip select generation ? 2 flexcan interfaces (2.0b active) with 32 message objects ? flexray module (v2.1 rev. a) with 2 channels, 64 message buffers and data rates up to 10 mbit/s two 12-bit analog-to-digital converters (adcs) ? 16 input channels ? programmable cross triggering unit (ctu) to synchronize adcs conversion with timer and pwm sine wave generator (d/a with low pass filter) on-chip can/uart bootstrap loader single 3.0 v to 3.6 v voltage supply ambient temperature range ?40 c to 125 c junction temperature range ?40 c to 150 c lqfp100 (14 x 14x 1.4 mm) lqfp144 (20 x 20 x 1.4 mm) www.st.com
contents spc56xl60/54 2/160 doc id 15457 rev 8 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.1 high-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.4 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . 13 1.5.5 on-chip flash memory with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.6 on-chip sram with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.7 platform flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.8 platform static ram controller (sramc) . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.9 memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.10 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.11 peripheral bridge (pbridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.12 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.13 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.14 frequency-modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . 18 1.5.15 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.16 internal reference clock ( rc) oscillator . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.17 clock, reset, power, mode and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.18 periodic interrupt timer module (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.19 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.20 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.21 fault collection and control unit (fccu) . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.22 system integration unit lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.23 non-maskable interrupt (nmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.24 boot assist module (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.25 system status and configuration module (sscm) . . . . . . . . . . . . . . . . 21 1.5.26 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.27 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
spc56xl60/54 contents doc id 15457 rev 8 3/160 1.5.28 serial communication interface module (linflexd) . . . . . . . . . . . . . . . . 24 1.5.29 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . . . 24 1.5.30 flexpwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.31 etimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.32 sine wave generator (swg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.33 analog-to-digital converter module (adc) . . . . . . . . . . . . . . . . . . . . . . 27 1.5.34 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.35 cyclic redundancy checker (crc) unit . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.36 redundancy control and checker unit (rccu) . . . . . . . . . . . . . . . . . . 29 1.5.37 junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.38 nexus port controller (npc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.39 ieee 1149.1 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5.40 voltage regulator / power management unit (pmu) . . . . . . . . . . . . . . . 31 1.5.41 built-in self-test (bist) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 33 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.4.1 general notes for specifications at maximum junction temperature . . 101 3.5 electromagnetic interference (emi) charac teristics . . . . . . . . . . . . . . . . 102 3.6 electrostatic discharge (esd) characteristics . . . . . . . . . . . . . . . . . . . . 103 3.7 static latch-up (lu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.8 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 104 3.9 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.10 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.11 temperature sensor electrical characterist ics . . . . . . . . . . . . . . . . . . . . 111 3.12 main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 111
contents spc56xl60/54 4/160 doc id 15457 rev 8 3.13 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.14 16 mhz rc oscillator electrical characterist ics . . . . . . . . . . . . . . . . . . . 114 3.15 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.15.1 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.16 flash memory electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.17 swg electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.18 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.18.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.19 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.19.1 reset sequence duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.19.2 reset sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.19.3 reset sequence trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.19.4 reset sequence ? start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.19.5 external watchdog window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.20 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.20.1 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.20.2 wkup/nmi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.20.3 ieee 1149.1 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.20.4 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.20.5 external interrupt timing (irq pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.20.6 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
spc56xl60/54 list of tables doc id 15457 rev 8 5/160 list of tables table 1. spc56xl60/54 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. platform memory access time summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. lqfp100 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 4. lqfp144 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 table 5. lfbga257 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6. supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 7. system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 8. pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 10. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 11. thermal characteristics for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 12. thermal characteristics for lqfp144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 13. thermal characteristics for lfbga257 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 14. emi configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 15. emi emission testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 16. esd ratings , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 17. latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 18. recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 19. voltage regulator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 05 table 20. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 21. current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 table 22. temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 23. main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 24. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 25. rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 26. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 27. flash memory program and erase electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 120 table 28. flash memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 29. flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 30. mpc5643l swg specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 31. pad ac specifications (3.3 v , ipp_hve = 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 32. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 33. reset sequence trigger ? reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 34. voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 35. reset electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 36. wkup/nmi glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 37. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 31 table 38. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 39. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 40. dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 41. lqfp100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 42. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 43. lfbga257 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 44. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
list of figures spc56xl60/54 6/160 doc id 15457 rev 8 list of figures figure 1. spc56xl60/54 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 3. spc56xl60/54 lqfp144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4. spc56xl60/54 lfbga257 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5. bcp68 board schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 6. crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 7. main oscillator electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 8. adc characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 9. input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 10. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 11. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 12. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 13. destructive reset sequence, bist enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 14. destructive reset sequence, bist disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 15. external reset sequence long, bist enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 16. functional reset sequence long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 figure 17. functional reset sequence short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 figure 18. reset sequence start for destructive resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 19. reset sequence start via reset assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 20. reset sequence - external watchdog trigger window position . . . . . . . . . . . . . . . . . . . . . 129 figure 21. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 22. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 23. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 24. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 25. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 26. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 27. nexus evti input pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 28. nexus double data rate (ddr) mode output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 29. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 30. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 31. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 32. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 33. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 34. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 35. dspi modified transfer format timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . 140 figure 36. dspi modified transfer format timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . 141 figure 37. dspi modified transfer format timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 38. dspi modified transfer format timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 39. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 42 figure 40. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 41. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 42. lfbga257 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 43. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 49
spc56xl60/54 introduction doc id 15457 rev 8 7/160 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. this document provides electrical specific ations, pin assignments, and package diagrams for the spc56xl60/54 series of microcontroller units (mcus). for functional characteristics, see the spc56xl60/54 microcontroller reference manual . for use of the spc56xl60/54 in a fail-safe system according to safety standard iec 61508, see the safety application guide for spcel60. 1.2 description the leopard series microcontrollers are system-on-chip devices that are built on power architecture technology and contain enhancements that improve the architecture?s fit in embedded applications, include additional inst ruction support for digital signal processing (dsp) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, controller area network, and an enhanced modular input-output system. the spc56xl60/54 family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. it belongs to an expanding range of automotive-focused products designed to address electrical hydr aulic power steering (ehps), electric power steering (eps) and airbag app lications. the advanced and co st-efficient host processor core of the spc56xl60/54 automotive controller family complies with the power architecture embedded category. it operates at speeds as high as 120 mhz and offers high- performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users? implementations. 1.3 device comparison
introduction spc56xl60/54 8/160 doc id 15457 rev 8 table 1. spc56xl60/54 device summary feature spc56el60 spc56el54 cpu ty p e 2 e200z4 (in lock-step or decoupled operation) 2 e200z4 (in lock-step or decoupled operation) architecture harvard harvard execution speed 0?120 mhz (+2% fm) 0?120 mhz (+2% fm) dmips intrinsic performance >240 mips >240 mips simd (dsp + fpu) yes yes mmu 16 entry 16 entry instruction set ppc yes yes instruction set vle yes yes instruction cache 4 kb, edc 4 kb, edc mpu-16 regions yes, replicated module yes, replicated module semaphore unit (sema4) yes yes buses core bus ahb, 32-bit address, 64-bit data ahb, 32-bit address, 64-bit data internal periphery bus 32-bit address, 32-bit data 32-bit address, 32-bit data crossbar master slave ports lock step mode: 4 3 decoupled parallel mode: 6 3 lock step mode: 4 3 decoupled parallel mode: 6 3 memory flash 1 mb, ecc, rww 768 k, ecc, rww static ram (sram) 128 kb, ecc 96 kb, ecc
spc56xl60/54 introduction doc id 15457 rev 8 9/160 modules interrupt controller (intc) 16 interrupt levels, replicated module 16 interrupt levels, replicated module periodic interrupt timer (pit) 1 4 channels 1 4 channels system timer module (stm) 1 4 channels, replicated module 1 4 channels, replicated module software watchdog timer (swt) yes, replicated module yes, replicated module edma 16 channels, replicated module 16 channels, replicated module flexray 1 64 message buffers, dual channel 1 64 message buffers, dual channel flexcan 2 32 message buffers 2 32 message buffers linflexd (uart and lin with dma support) 22 clock out yes yes fault collection and control unit (fccu) ye s ye s cross triggering unit (ctu) yes yes etimer 3 6 channels (1) 3 6 channels (1) flexpwm 2 module 4 (2 + 1) channels (2) 2 module 4 (2 + 1) channels (2) analog-to-digital converter (adc) 2 12-bit adc, 16 channels per adc (3 internal, 4 shared and 9 external) 2 12-bit adc, 16 channels per adc (3 internal, 4 shared and 9 external) sine wave generator (swg) 32 point 32 point modules (cont.) deserial serial peripheral interface (dspi) 3 dspi as many as 8 chip selects 3dspi as many as 8 chip selects cyclic redundancy checker (crc) unit ye s ye s junction temperature sensor (tsens) yes, replicated module yes, replicated module digital i/os 16 16 supply device power supply 3.3 v with integrated bypassable ballast transistor external ballast transistor not needed for bare die 3.3 v with integrated bypassable ballast transistor external ballast transistor not needed for bare die analog reference voltage 3.0 v ? 3.6 v and 4.5 v ? 5.5 v 3.0 v ? 3.6 v and 4.5 v ? 5.5 v clocking frequency-modulated phase- locked loop (fmpll) 22 internal rc oscillator 16 mhz 16 mhz external crystal oscillator 4?40mhz 4?40mhz table 1. spc56xl60/54 device summary (continued) feature spc56el60 spc56el54
introduction spc56xl60/54 10/160 doc id 15457 rev 8 1.4 block diagram figure 1 shows a top-level block diagram of the spc56xl60/54 device. debug nexus level 3+ level 3+ packages lqfp 100 pins 144 pins 100 pins 144 pins lbga (3) lbga257 lbga257 temperature temperature range (junction) ?40 to 150 c ?40 to 150 c ambient temperature range using external ballast transistor (lqfp) ?40 to 125 c ?40 to 125 c 1. the third etimer (etimer_2) is avai lable with external i/o access only in the bga package, on the lqfp package etimer_2 is available internally on ly without any external i/o access. 2. the second flexpwm module is av ailable only in the bga package. 3. lbga257 available only as development package. table 1. spc56xl60/54 device summary (continued) feature spc56el60 spc56el54
spc56xl60/54 introduction doc id 15457 rev 8 11/160 figure 1. spc56xl60/54 block diagram adc ? analog-to-digital converter bam ? boot assist module cmu ? clock monitoring unit crc ? cyclic redundancy check unit ctu ? cross triggering unit dspi ? serial peripherals interface ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller fccu ? fault collection and control unit flexcan ? controller area network controller fmpll ? frequency modulated phase locked loop intc ? interrupt controller ircosc ? internal rc oscillator jtag ? joint test action group interface linflexd ? lin controller with dma support mc ? mode entry, clock, reset, & power pbridge ? peripheral bridge pit ? periodic interrupt timer pmu ? power management unit rc ? redundancy checker rtc ? real time clock sema4 ? semaphore unit siul ? system integration unit lite sscm ? system status and configuration module stm ? system timer module swg ? sine wave generator swt ? software watchdog timer tsens ? temperature sensor xosc ? crystal oscillator sram pmu swt ecsm stm intc edma crossbar switch vle mmu i-cache spe e200z4 vle mmu i-cache spe e200z4 memory protection unit crossbar switch memory protection unit pbridge jtag nexus jtag nexus rc rc rc rc flexray pbridge tsens tsens ecc bits flash memory ecc bits + logic siul mc wakeup adc adc xosc bam sscm secondary fmpll fmpll ircosc cmu cmu ctu pit fccu flexpwm flexpwm etimer etimer etimer flexcan flexcan linflexd linflexd dspi dspi dspi crc cmu sema4 swt ecsm stm intc edma sema4 swg ecc logic for sram ecc logic for sram
introduction spc56xl60/54 12/160 doc id 15457 rev 8 1.5 feature details 1.5.1 high-performance e200z4d core the e200z4d power architecture ? core provides the following features: 2 independent execution units, both supporting fixed-point and floating-point operations dual issue 32-bit power arch itecture techno logy compliant ? 5-stage pipeline (if, dec, ex1, ex2, wb) ? in-order execution and instruction retirement full support for power architecture instruction set and variable length encoding (vle) ? mix of classic 32-bit and 16-bit instruction allowed ? optimization of code size possible thirty-two 64-bit general purpose registers (gprs) harvard bus (32-bit address, 64-bit data) ? i-bus interface capable of one outstanding transaction plus one piped with no wait- on-data return ? d-bus interface capable of two tran sactions outstanding to fill ahb pipe i-cache and i-ca che controller ? 4 kb, 256-bit cache line (programmable for 2- or 4-way) no data cache 16-entry mmu 8-entry branch table buffer branch look-ahead instruction buffer to accelerate branching dedicated branch address calculator 3 cycles worst case for missed branch load/store unit ? fully pipelined ? single-cycle load latency ? big- and little-endian modes supported ? misaligned access support ? single stall cycle on load to use single-cycle throughput (2 -cycle latency) integer 32 32 multiplication 4 ? 14 cycles integer 32 32 division (avera ge division on various benchmark of nine cycles) single precision floating-point unit ? 1 cycle throughput (2-cycle latency) floating-point 32 32 multiplication ? target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 32 division ? special square root and min/max function implemented signal processing support: apu-spe 1.1 ? support for vectorized mode: as many as two floating-point instructions per clock vectored interrupt support reservation instruction to support read-modify-write constructs
spc56xl60/54 introduction doc id 15457 rev 8 13/160 extensive system development and tracing support via nexus debug port 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. the crossbar provides the following features: 4 masters and 3 slaves supported per each replicated crossbar ? masters allocation for each crossbar: e200z4d core with two independent bus interface units (biu) for i and d access (2 masters), one edma, one flexray ? slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle instructio n and data array, one redundant sram controller with 1 slave port each and 1 redundant peripheral bus bridge 32-bit address bus and 64-bit data bus programmable arbitration priority ? requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method, based upon the id of the last master to be granted access or a priority order can be assigned by software at application run time temporary dynamic priority elevation of masters the xbar is replicated for each processing channel. 1.5.3 memory protection unit (mpu) the memory protection unit splits the physical memory into 16 different regions. each master (edma, flexray, cpu) can be assigned different access rights to each region. 16-region mpu with concurrent checks against each master access 32-byte granularity for protected address region the memory protection unit is replicated for each processing channel. 1.5.4 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware microarchitecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is used to minimize the overall block size.
introduction spc56xl60/54 14/160 doc id 15457 rev 8 the edma module provides the following features: 16 channels supporting 8-, 16-, and 32-bit value single or block transfers support variable sized queues and circular buffered queue source and destination address registers independently configured to post-increment or stay constant support major and minor loop offset support minor and major loop done signals dma task initiated either by hardware requestor or by software each dma task can optionally generate an interrupt at completion and retirement of the task signal to indicate closure of last minor loop transfer control descriptors mapped inside the sram the edma controller is replicated for each processing channel. 1.5.5 on-chip flash memory with ecc this device includes programmable, non-volatile flash memory. the non-volatile memory (nvm) can be used for instruction storage or data storage, or both. the flash memory module interfaces with the system bus through a dedicated flash memory array controller. it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains four 128-bit prefetch buffers. prefetch buffer hits allow no-wait responses. buffer misses incur a 3 wait state response at 120 mhz. the flash memory module provides the following features up to 1 mb of flash memory in un ique multi-partitioned hard macro sectorization: ? 1 mb: 16 kb + 2 48 kb + 16 kb + 2 64 kb + 2 128 kb + 2 256 kb ? 768 kb: 16 kb + 2 48 kb + 16 kb + 2 64 kb + 2 128 kb + 1 256 kb eeprom emulation (in software) within sa me module but on different partition 16 kb test sector and 16 kb shadow block for test, censorship device and user option bits wait states: ? 3 wait states for frequencies =< 120 mhz ? 2 wait states for frequencies =< 80 mhz ? 1 wait state for frequencies =< 60 mhz flash memory line 128-bit wide with 8-bit ecc on 64-bit word (total 144 bits) accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations 1-bit error correction, 2-bit error detection 1.5.6 on-chip sram with ecc the spc56xl60/54 sram provides a general-purpose single port memory. ecc handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic coverage including the array internal address decoder.
spc56xl60/54 introduction doc id 15457 rev 8 15/160 the sram module provides the following features: system sram: 128 kb ecc on 32-bit word (syndrome of 7 bits) ? ecc covers sram bus address 1-bit error correction, 2-bit error detection wait states: ? 1 wait state for frequencies =< 120 mhz ? 0 wait states for frequencies =< 80 mhz 1.5.7 platform flash memory controller the following list summarizes the key features of the flash memory controller: single ahb port interface supports a 64-bit data bus. all ahb aligned and unaligned reads within the 32-bit container are supported. only aligned word writes are supported. array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank. code flash (bank0) interface provides configurable read buffering and page prefetch support. ? four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized flash access. single-cycle read responses (0 ah b data-phase wait states) fo r hits in the buffers. the buffers implement a least-recently-use d replacement algorithm to maximize performance. programmable response for read-while-write sequences including support for stall- while-write, optional stall notification interrupt, optional flash operation abort , and optional abort notification interrupt. separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. support of address-based read access timing for emulation of other memory types. support for reporting of single- and multi-bit error events. typical operating configuration loaded in to programming model by system reset. the platform flash controller is replicated for each processor. 1.5.8 platform static ram controller (sramc) the sramc module is the platform sram array controller, with integrated error detection and correction. the main features of the sramc provide connectivity for the following interfaces: xbar slave port (64-bit data path) ecsm (ecc error reporting, error injection and configuration) sram array
introduction spc56xl60/54 16/160 doc id 15457 rev 8 the following functions are implemented: ecc encoding (32-bit boundary for data and complete address bus) ecc decoding (32-bit boundary and entire address) address translation from the ahb prot ocol on the xbar to the sram array the platform sram controller is replicated for each processor. 1.5.9 memory subsystem access time every memory access the cpu performs requir es at least one system clock cycle for the data phase of the access. slower memories or peripherals may require additional data phase wait states. additional data phase wait states may also occur if the slave being accessed is not parked on the requesting master in the crossbar. ta bl e 2 shows the number of additional data phase wait states required for a range of memory accesses. 1.5.10 error correction status module (ecsm) the ecsm on this device manages the ecc configuration and reporting for the platform memories (flash memory and sram). it does not implement the actual ecc calculation. a detected error (double error for flash memory or sram) is also reported to the fccu. the following errors and indications are reported into the ecsm dedicated registers: ecc error status and configuration for flash memory and sram ecc error reporting for flash memory ecc error reporting for sram ecc error injection for sram table 2. platform memory access time summary ahb transfer data phase wait states description e200z4d instruction fetch 0 flash memory prefetch buffer hit (page hit) e200z4d instruction fetch 3 flash memory prefetch buffer miss (based on 4-cycle random flash array access time) e200z4d data read 0?1 sram read e200z4d data write 0 sram 32-bit write e200z4d data write 0 sram 64-bit write (executed as 2 x 32-bit writes) e200z4d data write 0?2 sram 8-,16-bit write (read-modify-write for ecc) e200z4d flash memory read 0 flash memory prefetch buffer hit (page hit) e200z4d flash memory read 3 flash memory prefetch buffer miss (at 120 mhz; includes 1 cycle of program flash memory controller arbitration)
spc56xl60/54 introduction doc id 15457 rev 8 17/160 1.5.11 peripheral bridge (pbridge) the pbridge implements the following features: duplicated periphery master access privilege level per peripheral (per master: read access enable; write access enable) checker applied on pbridge output toward periphery byte endianess swap capability 1.5.12 interrupt controller (intc) the intc provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. for high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. the intc supports the priority ceiling protoc ol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. the intc provides the following features: duplicated periphery unique 9-bit vector per interrupt source 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source priority elevation for shared resource the intc is replicated for each processor.
introduction spc56xl60/54 18/160 doc id 15457 rev 8 1.5.13 system clocks and clock generation the following list summarizes the system clock and clock generation on this device: lock status continuously monitored by lock detect circuitry loss-of-clock (loc) detection for reference and feedback clocks on-chip loop filter (for improved electromagnetic interference performance and fewer external components required) programmable output clock divider of system clock ( 1, 2, 4, 8) flexpwm module and as many as three etim er modules running on an auxiliary clock independent from system clock (with max frequency 120 mhz) on-chip crystal oscillator with automatic level control dedicated internal 16 mhz internal rc oscillator for rapid start-up ? supports automated frequency trimming by hardware during device startup and by user application auxiliary clock domain for motor control pe riphery (flexpwm, etimer, ctu, adc, and swg) 1.5.14 frequency-modulated phase-locked loop (fmpll) each device has two fmplls. each fmpll allows the user to generate high speed system clocks starting from a minimum reference of 4 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the fmpll multiplication factor, output clock divider ratio are all software configurable. the fmplls have the following major features: input frequency: 4?40 mhz co ntinuous range (limited by the crystal oscillator) voltage controlled oscillato r (vco) range: 256?512 mhz frequency modulation via software control to reduce and control emission peaks ? modulation depth 2% if centered or 0% to ?4% if downshifted via software control register ? modulation frequency: triangular modulation with 25 khz nominal rate option to switch modulation on and off via software interface output divider (odf) for reduced frequency operation without re-lock 3 modes of operation ? bypass mode ? normal fmpll mode with crystal reference (default) ? normal fmpll mode with external reference lock monitor circuitry with lock status loss-of-lock detection for reference and feedback clocks self-clocked mode (scm) operation on-chip loop filter
spc56xl60/54 introduction doc id 15457 rev 8 19/160 auxiliary fmpll ? used for flexray due to precise symbol rate requirement by the protocol ? used for motor control periphery and connected ip (a/d digital interface ctu) to allow independent frequencies of operation for pwm and timers and jitter-free control ? option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop ? allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than the syst em to ensure higher resolution 1.5.15 main oscillator the main oscillator prov ides these features: input frequency range 4?40 mhz crystal input mode external reference clock (3.3 v) input mode fmpll reference 1.5.16 internal referen ce clock (rc) oscillator the architecture uses constant current charging of a capacitor. the voltage at the capacitor is compared to the stable b andgap reference voltage. the rc oscillator is the device safe clock. the rc oscillator provides these features: nominal frequency 16 mhz 5% variation over voltage and temperature after process trim clock output of the rc oscillato r serves as system clock sour ce in case loss of lock or loss of clock is detected by the fmpll rc oscillator is used as the default system clock during startup and can be used as back-up input source of fmpll(s) in case xosc fails 1.5.17 clock, reset, pow er, mode and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) these modules provide the following: clock gating and clock distribution control halt, stop mode control flexible configurable system and auxiliary clock dividers various execution modes ? halt and stop mode as reduced activity low power mode ? reset, idle, test, safe ? various run modes with software selectable powered modules ? no stand-by mode implemented (no internal switchable power domains)
introduction spc56xl60/54 20/160 doc id 15457 rev 8 1.5.18 periodic interrupt timer module (pit) the pit module implements the following features: 4 general purpose interrupt timers 32-bit counter resolution can be used for software tick or dma trigger operation 1.5.19 system timer module (stm) the stm implements the following features: up-counter with 4 output compare registers os task protection and hardware tick implementation per autosar (a) requirement the stm is replicated for each processor. 1.5.20 software watchdog timer (swt) this module implements the following features: fault tolerant output safe internal rc oscillator as reference clock windowed watchdog program flow control monitor with 16-bit pseudorandom key generation allows a high level of safety (sil3 monitor) the swt module is replicated for each processor. 1.5.21 fault collection and control unit (fccu) the fccu module has the following features: redundant collection of hardware checker results redundant collection of error information and latch of faults from critical modules on the device collection of se lf-test results configurable and graded fault control ? internal reactions (no internal reaction, irq, functional reset, destructive reset, or safe mode entered) ? external reaction (failure is reported to the external/surrounding system via configurable output pins) 1.5.22 system integrat ion unit lite (siul) the siul controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. a. automotive open system architecture
spc56xl60/54 introduction doc id 15457 rev 8 21/160 the siu provides the following features: centralized pad control on a per-pin basis ? pin function selection ? configurable weak pull-up/down ? configurable slew rate control (slow/medium/fast) ? hysteresis on gpio pins ? configurable automatic safe mode pad control input filtering for external interrupts 1.5.23 non-maskable interrupt (nmi) the non-maskable interrupt with de-glitching filter supports high-priority core exceptions. 1.5.24 boot assist module (bam) the bam is a block of read-only memory with hard-coded content. the bam program is executed only if serial booting mode is selected via boot configuration pins. the bam provides the following features: enables booting via serial mode (flexcan or linflex-uart) supports programmable 64-bit password protection for serial boot mode supports serial bootloading of either power architecture code (default) or vle code automatic switch to serial boot mode if internal flash memory is blank or invalid 1.5.25 system status and configuration module (sscm) the sscm on this device features the following: system configuration and status debug port status and debug port enable multiple boot code starting locations out of reset through implementation of search for valid reset configuration half word sets up the mmu to allow user boot code to execute as either power architecture code (default) or as vle code out of flash memory triggering of device self-tests during reset phase of device boot 1.5.26 flexcan the flexcan module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth.
introduction spc56xl60/54 22/160 doc id 15457 rev 8 the flexcan module provides the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0 to 8 bytes data length ? programmable bit rate as fast as 1mbit/s 32 message buffers of 0 to 8 bytes data length each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id or lowest buffer number time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) high immunity to emi short latency time due to an arbitration scheme for high-priority messages transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to message id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo programmable clock source ? system clock ? direct oscillator clock to avoid fmpll jitter
spc56xl60/54 introduction doc id 15457 rev 8 23/160 1.5.27 flexray the flexray module provides the following features: full implementation of flexray protocol specification 2.1 rev. a 64 configurable message buffers can be handled dual channel or single channel mode of operation, each as fast as 10 mbit/s data rate message buffers configurable as transmit or receive message buffer size configurable message filtering for all message buffers based on frame id, cycle count, and message id programmable acceptance filters for receive fifo message buffer header, status, and payload data stored in system memory (sram) internal flexray memories have error detection and correction
introduction spc56xl60/54 24/160 doc id 15457 rev 8 1.5.28 serial communication interface module (linflexd) the linflexd module (linflex with dma suppor t) on this device features the following: supports lin master mode, lin slave mode and uart mode lin state machine compliant to lin1.3, 2.0, and 2.1 specifications manages lin frame transmission and reception without cpu intervention lin features ? autonomous lin frame handling ? message buffer to store as many as 8 data bytes ? supports messages as long as 64 bytes ? detection and flagging of lin errors (sync field, delimiter, id parity, bit framing, checksum and time-out errors) ? classic or extended checksum calculation ? configurable break duration of up to 50-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features (loop back, lin bus stuck dominant detection) ? interrupt driven operation with 16 interrupt sources lin slave mode features ? autonomous lin header handling ? autonomous lin response handling uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words) ? configurable parity scheme: none, odd, even, always 0 ? speed as fast as 2 mbit/s ? error detection and flagging (parity, noise and framing errors) ? interrupt driven operation with four interrupt sources ? separate transmitter and receiver cpu interrupt sources ? 16-bit programmable baud-rate modulus counter and 16-bit fractional ? two receiver wake-up methods support for dma enabled transfers 1.5.29 deserial serial peripheral interface (dspi) the dspi modules provide a synchronous serial interface for communication between the spc56xl60/54 and external devices.
spc56xl60/54 introduction doc id 15457 rev 8 25/160 a dspi module provides these features: full duplex, synchronous transfers master or slave operation programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag programmable transfer baud rate programmable data frames from 4 to 16 bits as many as 8 chip select lines available, depending on package and pin multiplexing 4 clock and transfer attributes registers chip select strobe available as alternate function on one of the chip select pins for de- glitching fifos for buffering as many as 5 transfers on the transmit and receive side queueing operation possible through use of the edma general purpose i/o functionality on pins when not used for spi 1.5.30 flexpwm the pulse width modulator module (flexpwm) contains four pwm channels, each of which is configured to control a single half-bridge power stage. two modules are included on lfbga257 devices; on the lqfp144 package, only one module is present. additionally, four fault input channels are provided per flexpwm module. this pwm is capable of controllin g most motor types, including: ac induction motors (acim) permanent magnet ac motors (pmac) brushless (bldc) and brush dc motors (bdc) switched (srm) and variable reluctance motors (vrm) stepper motors
introduction spc56xl60/54 26/160 doc id 15457 rev 8 a flexpwm module implements the following features: 16 bits of resolution for center, edge aligned, and asymmetrical pwms maximum operating frequency as high as 120 mhz ? clock source not modulated and independent from system clock (generated via secondary fmpll) fine granularity control for enhanced resolution of the pwm period pwm outputs can operate as complementary pairs or independent channels ability to accept signed numbers for pwm generation independent control of both edges of each pwm output synchronization to external hardware or other pwm supported double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability multiple adc trigger events can be generated per pwm cycle via hardware fault inputs can be assigned to control multiple pwm outputs programmable filter s for fault inputs independently programmable pwm output polarity independent top and bottom deadtime insertion each complementary pair can operate with its own pwm frequency and deadtime values individual software control for each pwm output all outputs can be forced to a value simultaneously pwmx pin can optionally output a third signal from each channel channels not used for pwm generation can be used for buffered output compare functions channels not used for pwm generation can be used for input capture functions enhanced dual edge capture functionality option to supply the source for each complementary pwm signal pair from any of the following: ? external digital pin ? internal timer channel ? external adc input, taking into account values set in adc high- and low-limit registers dma support
spc56xl60/54 introduction doc id 15457 rev 8 27/160 1.5.31 etimer module the mpc5643l provides three etimer modules (on the lqfp package etimer_2 is available internally only without any external i/o access). six 16-bit general purpose up/down timer/counters per module are implemented with the following features: maximum clock frequency of 120 mhz individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) maximum count rate ? equals peripheral clock divided by 2 for external event counting ? equals peripheral clock for internal clock counting cascadeable counters programmable count modulo quadrature deco de capabilities counters can share available input pins count once or repeatedly preloadable counters pins available as gpio when timer functionality not in use dma support 1.5.32 sine wave generator (swg) a digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver). 1.5.33 analog-to-digital converter module (adc) the adc module features include:
introduction spc56xl60/54 28/160 doc id 15457 rev 8 analog part: 2 on-chip adcs ? 12-bit resolution sar architecture ? same digital interface as in the spc560p family ? a/d channels: 9 external, 3 internal and 4 shared with other a/d (total 16 channels) ? one channel dedicated to each t-sensor to enable temperature reading during application ? separated reference for each adc ? shared analog supply voltage for both adcs ? one sample and hold unit per adc ? adjustable sampling and conversion time digital part: 4 analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location 2 modes of operation: cpu mode or ctu mode cpu mode features ? register based interface with the cpu: one result register per channel ? adc state machine managing three request flows: regular command, hardware injected command, software injected command ? selectable priority between software and hardware injected commands ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) ? dma compatible interface ctu mode features ? triggered mode only ? 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries) ? result alignment circuitry (lef t justified; ri ght justified) ? 32-bit read mode allows to have channel id on one of the 16-bit parts ? dma compatible interfaces built-in self-test features triggered by software 1.5.34 cross triggering unit (ctu) the adc cross triggering unit allows automatic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration.
spc56xl60/54 introduction doc id 15457 rev 8 29/160 the ctu implements the following features: cross triggering between adc, flexpwm, etimer, and external pins double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers maximum operating frequency less than or equal to 120 mhz trigger generation unit configurable in sequential mode or in triggered mode trigger delay unit to compensate the delay of external low pass filter double buffered global trigger unit allowing etimer synchronization and/or adc command generation double buffered adc command list pointers to minimize adc-trigger unit update double buffered adc conversion command list with as many as 24 adc commands each trigger capable of generating consecutive commands adc conversion command allows control of adc channel from each adc, single or synchronous sampling, independent result queue selection dma support with safety features 1.5.35 cyclic redundancy checker (crc) unit the crc module is a configurable multiple dat a flow unit to compute crc signatures on data written to its input register. the crc unit has the following features: 3 sets of registers to allow 3 concurrent contexts with possibly different crc computations, each with a selectable polynomial and seed computes 16- or 32-bit wide crc on the fly (single-cycle computation) and stores result in inte rnal register. the following standard crc polynomials are implemented: ?x 8 + x 4 + x 3 + x 2 + 1 [8-bit crc] ?x 16 +x 12 +x 5 + 1 [16-bit crc-ccitt] ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 [32-bit crc-ethernet(32)] key engine to be coupled with communica tion periphery where crc application is added to allow implementation of safe communication protocol offloads core from cycle-consuming crc and helps checking configuration signature for safe start-up or periodic procedures crc unit connected as peripheral bus on internal peripheral bus dma support 1.5.36 redundancy contro l and checker unit (rccu) the rccu checks all outputs of the sphere of replicat ion (addresses, data, control signals). it has the following features: duplicated module to guarantee highest possible diagnostic coverage (check of checker) multiple times replicated ips are used as checkers on the sor outputs
introduction spc56xl60/54 30/160 doc id 15457 rev 8 1.5.37 junction temperature sensor the junction temperature sensor provides a value via an adc channel that can be used by software to calculate the device junction temperature. the key parameters of the junction temperature sensor include: nominal temperature range from ?40 to 150 c software temperature alarm via analog adc comparator possible 1.5.38 nexus port controller (npc) the npc module provides real-time developmen t support capabilities for this device in compliance with the ieee-isto 5001-2003. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the npc block interfaces to the host processor and internal buses to provide development support as per the ieee-isto 5001-2003 class 3+, including selected features from class 4 standard. the development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the mcus internal memory map and access to the power architecture internal registers during halt. the nexus interface also supports a jtag only mode using only the jtag pins. the following features are implemented: full and reduced port modes mcko (message clock out) pin 4 or 12 mdo (message data out) pins (b) 2 mseo (message start/end out) pins evto (event out) pin ? auxiliary input port evti (event in) pin 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) ? supports jtag mode host processor (e200) development support features ? data trace via data write messaging (dwm) and data read messaging (drm). this allows the development tool to trace reads or writes, or both, to selected internal memory resources. ? ownership trace via ownership trace mess aging (otm). otm facilitates ownership trace by providing visibility of which pr ocess id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. ? program trace via branch trace mess aging (btm). branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, static code may be traced. b. 4 mdo pins on lqfp144 package, 12 mdo pins on lfbga257 package.
spc56xl60/54 introduction doc id 15457 rev 8 31/160 ? watchpoint messaging (wpm ) via the auxiliary port ? watchpoint trigger enable of program and/or data trace messaging ? data tracing of instruction fetches via private opcodes 1.5.39 ieee 1149.1 jtag controller (jtagc) the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ieee test access port (tap) interface with 5 pins: ?tdi ?tms ?tck ?tdo ?jcomp selectable modes of operation include jtagc/debug or normal system operation 5-bit instruction register that supports the follo wing ieee 1149.1 -2001 defined instructions: ? bypass ? idcode ?extest ?sample ? sample/preload 3 test data registers: a bypass register, a boundary scan register, and a device identification register. the size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths. tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry 1.5.40 voltage regulator / power management unit (pmu) the on-chip voltage regulator module provides the following features: single external rail required single high supply required: nominal 3.3 v both for packaged and known good die option ? packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) ? known good die option uses embedded balla st transistor as dissipation capacity is increased to reduce system cost all i/os are at same voltage as external supply (3.3 v nominal) duplicated low-voltage detectors (lvd) to guarantee proper operation at all stages (reset, configuration, normal operation) and, to maximize safety coverage, one lvd can be tested while the other operates (on-line self-testing feature)
introduction spc56xl60/54 32/160 doc id 15457 rev 8 1.5.41 built-in self-test (bist) capability this device includes the following protection against latent faults: boot-time memory built -in self-test (mbist) boot-time scan-based logic built-in self-test (lbist) run-time adc built-in self-test (bist) run-time built-in self test of lvds
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 33/160 2 package pinouts and signal descriptions 2.1 package pinouts figure 2 shows the lqfp100 pinout. figure 2. lqfp100 pinout figure 3 shows the spc56xl60/54 in the lqfp144 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 a[4] vpp_test d[14] c[14] c[13] d[12] vdd_hv_fla vss_hv_fla vdd_hv_reg_1 vss_lv_cor vdd_lv_cor a[3] vdd_hv_io vss_hv_io b[4] tck tms b[5] a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] fccu_f[0] vdd_lv_cor vss_lv_cor b[7] b[8] e[2] vdd_hv_adr0 vss_hv_adr0 b[9] b[10] b[11] b[12] vdd_hv_adr1 vss_hv_adr1 vdd_hv_adv vss_hv_adv b[13] b[14] c[0] e[0] bctrl vdd_lv_cor vss_lv_cor vdd_hv_pmu a[15] a[14] c[6] fccu_f[1] b[6] a[13] a[9] vss_lv_cor vdd_lv_cor vdd_hv_reg_2 d[4] d[3] vss_hv_io vdd_hv_io d[0] c[15] jcomp a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] lqfp100 package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 lqfp100 package nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] vdd_hv_reg_0 vss_lv_cor vdd_lv_cor vdd_hv_io vss_hv_io d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_pll0_pll1 vdd_lv_pll0_pll1
package pinouts and signal descriptions spc56xl60/54 34/160 doc id 15457 rev 8 figure 3. spc56xl60/54 lqfp144 pinout (top view) figure 4 shows the spc56xl60/54 in the lfbga257 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 a[4] vpp_test f[12] d[14] g[3] c[14] g[2] c[13] g[4] d[12] g[6] vdd_hv_fla vss_hv_fla vdd_hv_reg_1 vss_lv_cor vdd_lv_cor a[3] vdd_hv_io vss_hv_io b[4] tck tms b[5] g[5] a[2] g[7] c[12] g[8] c[11] g[9] d[11] g[10] d[10] g[11] a[1] a[0] d[7] fccu_f[0] vdd_lv_cor vss_lv_cor c[1] e[4] b[7] e[5] c[2] e[6] b[8] e[7] e[2] vdd_hv_adr0 vss_hv_adr0 b[9] b[10] b[11] b[12] vdd_hv_adr1 vss_hv_adr1 vdd_hv_adv vss_hv_adv b[13] e[9] b[15] e[10] b[14] e[11] c[0] e[12] e[0] bctrl vdd_lv_cor vss_lv_cor vdd_hv_pmu a[15] a[14] c[6] fccu_f[1] d[2] f[3] b[6] vss_lv_cor a[13] vdd_lv_cor a[9] f[0] vss_lv_cor vdd_lv_cor vdd_hv_reg_2 d[4] d[3] vss_hv_io vdd_hv_io d[0] c[15] jcomp a[12] e[15] a[11] e[14] a[10] e[13] b[3] f[14] b[2] f[15] f[13] c[10] b[1] b[0] lqfp144 package nmi a[6] d[1] f[4] f[5] vdd_hv_io vss_hv_io f[6] mdo0 a[7] c[4] a[8] c[5] a[5] c[7] vdd_hv_reg_0 vss_lv_cor vdd_lv_cor f[7] f[8] vdd_hv_io vss_hv_io f[9] f[10] f[11] d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_pll0_pll1 vdd_lv_pll0_pll1
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 35/160 figure 4. spc56xl60/54 lfbga257 pinout (top view) table 3 (lqfp100 pin function summary) , ta bl e 4 , and ta bl e 5 provide the pin function summaries for the 100-pin, 144-pin, and 257-pin packages, respectively, listing all the signals multiplexed to each pin. 1234567891011121314151617 a v ss_hv _io v ss_hv _io v dd_hv _io h[2] h[0] g[14] d[3] c[15] v dd_hv _io a[12] h[10] h[14] a[10] b[2] c[10] v ss_hv _io v ss_hv _io b v ss_hv _io v ss_hv _io b[6] a[14] f[3] a[9] d[4] d[0] v ss_hv _io h[12] e[15] e[14] b[3] f[13] b[0] v dd_hv _io v ss_hv _io c v dd_hv _io nc (1) v ss_hv _io fccu_ f[1] d[2] a[13] v dd_hv _reg_2 v dd_hv _reg_2 i[0] jcomp h[11] i[1] f[14] b[1] v ss_hv _io a[4] f[12] d f[5] f[4] a[15] c[6] v ss_lv_ cor v dd_lv_ cor f[0] v dd_hv _io v ss_hv _io nc a[11] e[13] f[15] v dd_hv _io v pp _test d[14] g[3] e mdo0 f[6] d[1] nmi nc c[14] g[2] i[3] f h[1] g[12] a[7] a[8] v dd_lv_ cor v dd_lv_ cor v dd_lv_ cor v dd_lv_ cor v dd_lv_ cor v dd_lv_ cor v dd_lv_ cor nc c[13] i[2] g[4] g h[3] v dd_hv _io c[5] a[6] v dd_lv_ cor v ss_lv_ cor v ss_lv_ cor v ss_lv_ cor v ss_lv_ cor v ss_lv_ cor v dd_lv_ cor d[12] h[13] h[9] g[6] h g[13] v ss_hv _io c[4] a[5] v dd_lv v ss_lv v ss_lv v ss_lv v ss_lv v ss_lv v dd_lv v ss_lv v dd_hv _reg_1 v dd_hv _fla h[6] j f[7] g[15] v dd_hv _reg_0 v dd_hv _reg_0 v dd_lv v ss_lv v ss_lv v ss_lv v ss_lv v ss_lv v dd_lv v dd_lv v dd_hv _reg_1 v ss_hv _fla h[15] k f[9] f[8] c[7] v dd_lv v ss_lv v ss_lv v ss_lv v ss_lv v ss_lv v dd_lv nc h[8] h[7] a[3] l f[10] f[11] d[9] nc v dd_lv v ss_lv v ss_lv v ss_lv v ss_lv v ss_lv v dd_lv nc tck h[4] b[4] m v dd_hv _osc v dd_hv _io d[8] nc v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv c[11] b[5] tms h[5] n xtal v ss_hv _io d[5] v ss_lv_ pll nc c[12] a[2] g[5] p v ss_hv _osc reset d[6] v dd_lv_ pll v dd_lv_ cor v ss_lv_ cor b[8] nc v ss_hv _io v dd_hv _io b[14] v dd_lv_ cor v ss_lv_ cor v dd_hv _io g[10] g[8] g[7] r extal fccu _f[0] v ss_hv _io d[7] b[7] e[6] v dd_hv _adr0 b[10] v dd_hv _adr1 b[13] b[15] c[0] bctrl a[1] v ss_hv _io d[11] g[9] t v ss_hv _io v dd_hv _io nc c[1] e[5] e[7] v ss_hv _adr0 b[11] v ss_hv _adr1 e[9] e[10] e[12] e[0] a[0] d[10] v dd_hv _io v ss_hv _io u v ss_hv _io v ss_hv _io nc e[4] c[2] e[2] b[9] b[12] v dd_hv _adv v ss_hv _adv e[11] nc nc v dd_hv _pmu g[11] v ss_hv _io v ss_hv _io 1234567891011121314151617 1. nc = not connected (the pin is physical ly not connected to anything on the device)
package pinouts and signal descriptions spc56xl60/54 36/160 doc id 15457 rev 8 table 3. lqfp100 pin function summary pin # port/function peripheral ou tput function input function 1nmi ? 2a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] 3d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx 4a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] 5c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] 6a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] 7c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] 8a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] 9c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin 10 v dd_hv_reg_0 ? 11 v ss_lv_cor ?
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 37/160 12 v dd_lv_cor ? 13 v dd_hv_io ? 14 v ss_hv_io ? 15 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? 16 v dd_hv_osc ? 17 v ss_hv_osc ? 18 xtal ? 19 extal ? 20 reset ? 21 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] 22 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] 23 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] 24 v ss_lv_pll0_pll1 ? 25 v dd_lv_pll0_pll1 ? 26 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? 27 fccu_f[0] fccu f[0] f[0] 28 v dd_lv_cor ? 29 v ss_lv_cor ? 30 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 38/160 doc id 15457 rev 8 31 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] 32 e[2] siul ? gpio[66] adc_0 ? an[5] 33 v dd_hv_adr0 ? 34 v ss_hv_adr0 ? 35 b[9] siul ? gpio[25] adc_0 ?an[11] adc_1 36 b[10] siul ? gpio[26] adc_0 ?an[12] adc_1 37 b[11] siul ? gpio[27] adc_0 ?an[13] adc_1 38 b[12] siul ? gpio[28] adc_0 ?an[14] adc_1 39 v dd_hv_adr1 ? 40 v ss_hv_adr1 ? 41 v dd_hv_adv ? 42 v ss_hv_adv ? 43 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] 44 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] 45 c[0] siul ? gpio[32] adc_1 ? an[3] 46 e[0] siul ? gpio[64] adc_1 ? an[5] 47 bctrl ? table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 39/160 48 v dd_lv_cor ? 49 v ss_lv_cor ? 50 v dd_hv_pmu ? 51 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] 52 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] 53 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] 54 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] 55 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? 56 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? 57 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] 58 b[5] siul gpio[21] gpio[21] jtagc ? tdi 59 tms ? 60 tck ? 61 b[4] siul gpio[20] gpio[20] jtagc tdo ? table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 40/160 doc id 15457 rev 8 62 v ss_hv_io ? 63 v dd_hv_io ? 64 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] 65 v dd_lv_cor ? 66 v ss_lv_cor ? 67 v dd_hv_reg_1 ? 68 v ss_hv_fla ? 69 v dd_hv_fla ? 70 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd 71 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 72 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? 73 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] 74 v pp_test (1) ? 75 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 41/160 76 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] 77 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] 78 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] 79 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] debug[2] siul ? eirq[17] 80 b[3] siul gpio[19] gpio[19] sscm debug[3] debug[3] linflexd_0 ? rxd 81 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] 82 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 42/160 doc id 15457 rev 8 83 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] 84 jcomp ? ? jcomp 85 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 86 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] 87 v dd_hv_io ? 88 v ss_hv_io ? 89 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] 90 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] 91 v dd_hv_reg_2 ? 92 v dd_lv_cor ? 93 v ss_lv_cor ? 94 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 43/160 95 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] 96 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] 97 fccu_f[1] fccu f[1] f[1] 98 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] 99 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] 100 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] 1. v pp_test should always be tied to ground (v ss ) for normal operations. table 4. lqfp144 pin function summary pin # port/function peripheral ou tput function input function 1nmi ? 2a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] table 3. lqfp100 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 44/160 doc id 15457 rev 8 3d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx 4f[4] siul gpio[84] gpio[84] npc mdo[3] ? 5f[5] siul gpio[85] gpio[85] npc mdo[2] ? 6v dd_hv_io ? 7v ss_hv_io ? 8f[6] siul gpio[86] gpio[86] npc mdo[1] ? 9mdo0 ? 10 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] 11 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] 12 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] 13 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] 14 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 45/160 15 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin 16 v dd_hv_reg_0 ? 17 v ss_lv_cor ? 18 v dd_lv_cor ? 19 f[7] siul gpio[87] gpio[87] npc mcko ? 20 f[8] siul gpio[88] gpio[88] npc mseo[1] ? 21 v dd_hv_io ? 22 v ss_hv_io ? 23 f[9] siul gpio[89] gpio[89] npc mseo[0] ? 24 f[10] siul gpio[90] gpio[90] npc evto ? 25 f[11] siul gpio[91] gpio[91] npc ? evti 26 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? 27 v dd_hv_osc ? 28 v ss_hv_osc ? 29 xtal ? 30 extal ? 31 reset ? 32 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] 33 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 46/160 doc id 15457 rev 8 34 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] 35 v ss_lv_pll0_pll1 ? 36 v dd_lv_pll0_pll1 ? 37 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? 38 fccu_f[0] fccu f[0] f[0] 39 v dd_lv_cor ? 40 v ss_lv_cor ? 41 c[1] siul ? gpio[33] adc_0 ? an[2] 42 e[4] siul ? gpio[68] adc_0 ? an[7] 43 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] 44 e[5] siul ? gpio[69] adc_0 ? an[8] 45 c[2] siul ? gpio[34] adc_0 ? an[3] 46 e[6] siul ? gpio[70] adc_0 ? an[4] 47 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] 48 e[7] siul ? gpio[71] adc_0 ? an[6] 49 e[2] siul ? gpio[66] adc_0 ? an[5] 50 v dd_hv_adr0 ? 51 v ss_hv_adr0 ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 47/160 52 b[9] siul ? gpio[25] adc_0 adc_1 ?an[11] 53 b[10] siul ? gpio[26] adc_0 adc_1 ?an[12] 54 b[11] siul ? gpio[27] adc_0 adc_1 ?an[13] 55 b[12] siul ? gpio[28] adc_0 adc_1 ?an[14] 56 v dd_hv_adr1 ? 57 v ss_hv_adr1 ? 58 v dd_hv_adv ? 59 v ss_hv_adv ? 60 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] 61 e[9] siul ? gpio[73] adc_1 ? an[7] 62 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] 63 e[10] siul ? gpio[74] adc_1 ? an[8] 64 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] 65 e[11] siul ? gpio[75] adc_1 ? an[4] 66 c[0] siul ? gpio[32] adc_1 ? an[3] 67 e[12] siul ? gpio[76] adc_1 ? an[6] table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 48/160 doc id 15457 rev 8 68 e[0] siul ? gpio[64] adc_1 ? an[5] 69 bctrl ? 70 v dd_lv_cor ? 71 v ss_lv_cor ? 72 v dd_hv_pmu ? 73 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] 74 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] 75 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] 76 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] 77 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] 78 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] 79 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] 80 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 49/160 81 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] 82 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? 83 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] 84 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] 85 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? 86 b[5] siul gpio[21] gpio[21] jtagc ? tdi 87 tms ? 88 tck ? 89 b[4] siul gpio[20] gpio[20] jtagc tdo ? 90 v ss_hv_io ? 91 v dd_hv_io ? 92 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] 93 v dd_lv_cor ? 94 v ss_lv_cor ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 50/160 doc id 15457 rev 8 95 v dd_hv_reg_1 ? 96 v ss_hv_fla ? 97 v dd_hv_fla ? 98 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] 99 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd 100 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] 101 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 102 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? 103 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? 104 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] 105 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] 106 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] 107 v pp_test (1) ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 51/160 108 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] 109 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] 110 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] 111 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] 112 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] 113 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd 114 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] 115 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? 116 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 52/160 doc id 15457 rev 8 117 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] 118 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] 119 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] 120 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] 121 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] 122 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] 123 jcomp ? ? jcomp 124 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 53/160 125 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] 126 v dd_hv_io ? 127 v ss_hv_io ? 128 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] 129 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] 130 v dd_hv_reg_2 ? 131 v dd_lv_cor ? 132 v ss_lv_cor ? 133 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] 134 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] 135 v dd_lv_cor ? 136 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] 137 v ss_lv_cor ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 54/160 doc id 15457 rev 8 138 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] 139 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? 140 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx 141 fccu_f[1] fccu f[1] f[1] 142 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] 143 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] 144 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] 1. v pp_test should always be tied to ground (v ss ) for normal operations. table 5. lfbga257 pin function summary pin # port/function peripheral ou tput function input function a1 v ss_hv_io_ring ? a2 v ss_hv_io_ring ? a3 v dd_hv_io_ring ? a4 h[2] siul gpio[114] gpio[114] npc mdo[5] ? table 4. lqfp144 pin function summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 55/160 a5 h[0] siul gpio[112] gpio[112] npc mdo[7] ? a6 g[14] siul gpio[110] gpio[110] npc mdo[9] ? a7 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] a8 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync a9 v dd_hv_io_ring ? a10 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] a11 h[10] siul gpio[122] gpio[122] flexpwm_1 x[2] x[2] etimer_2 etc[2] etc[2] a12 h[14] siul gpio[126] gpio[126] flexpwm_1 a[3] a[3] etimer_2 etc[4] etc[4] a13 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] a14 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 56/160 doc id 15457 rev 8 a15 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] a16 v ss_hv_io_ring ? a17 v ss_hv_io_ring ? b1 v ss_hv_io_ring ? b2 v ss_hv_io_ring ? b3 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] b4 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] b5 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? b6 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] b7 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] b8 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] b9 v ss_hv_io_ring ? b10 h[12] siul gpio[124] gpio[124] flexpwm_1 b[2] b[2] table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 57/160 b11 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] b12 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] b13 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd b14 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] b15 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] b16 v dd_hv_io_ring ? b17 v ss_hv_io_ring ? c1 v dd_hv_io_ring ? c2 not connected ? c3 v ss_hv_io_ring ? c4 fccu_f[1] fccu f[1] f[1] c5 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx c6 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] c7 v dd_hv_reg_2 ? c8 v dd_hv_reg_2 ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 58/160 doc id 15457 rev 8 c9 i[0] siul gpio[128] gpio[128] etimer_2 etc[0] etc[0] dspi_0 cs4 ? flexpwm_1 ? fault[0] c10 jcomp ? ? jcomp c11 h[11] siul gpio[123] gpio[123] flexpwm_1 a[2] a[2] c12 i[1] siul gpio[129] gpio[129] etimer_2 etc[1] etc[1] dspi_0 cs5 ? flexpwm_1 ? fault[1] c13 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? c14 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] c15 v ss_hv_io_ring ? c16 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] c17 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] d1 f[5] siul gpio[85] gpio[85] npc mdo[2] ? d2 f[4] siul gpio[84] gpio[84] npc mdo[3] ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 59/160 d3 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] d4 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] d5 v ss_lv_core_ring ? d6 v dd_lv_core_ring ? d7 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] d8 v dd_hv_io_ring ? d9 v ss_hv_io_ring ? d10 not connected ? d11 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] d12 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] d13 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd d14 v dd_hv_io_ring ? d15 v pp_test (1) ? d16 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 60/160 doc id 15457 rev 8 d17 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] e1 mdo0 ? e2 f[6] siul gpio[86] gpio[86] npc mdo[1] ? e3 d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx e4 nmi ? e14 not connected ? e15 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? e16 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? e17 i[3] siul gpio[131] gpio[131] etimer_2 etc[3] etc[3] dspi_0 cs7 ? ctu_0 ext_tgr ? flexpwm_1 ? fault[3] f1 h[1] siul gpio[113] gpio[113] npc mdo[6] ? f2 g[12] siul gpio[108] gpio[108] npc mdo[11] ? f3 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] f4 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] f6 v dd_lv_core_ring ? f7 v dd_lv_core_ring ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 61/160 f8 v dd_lv_core_ring ? f9 v dd_lv_core_ring ? f10 v dd_lv_core_ring ? f11 v dd_lv_core_ring ? f12 v dd_lv_core_ring ? f14 not connected ? f15 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync f16 i[2] siul gpio[130] gpio[130] etimer_2 etc[2] etc[2] dspi_0 cs6 ? flexpwm_1 ? fault[2] f17 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] g1 h[3] siul gpio[115] gpio[115] npc mdo[4] ? g2 v dd_hv_io_ring ? g3 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] g4 a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] g6 v dd_lv_core_ring ? g7 v ss_lv_core_ring ? g8 v ss_lv_core_ring ? g9 v ss_lv_core_ring ? g10 v ss_lv_core_ring ? g11 v ss_lv_core_ring ? g12 v dd_lv_core_ring ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 62/160 doc id 15457 rev 8 g14 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd g15 h[13] siul gpio[125] gpio[125] flexpwm_1 x[3] x[3] etimer_2 etc[3] etc[3] g16 h[9] siul gpio[121] gpio[121] flexpwm_1 b[1] b[1] dspi_0 cs7 ? g17 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] h1 g[13] siul gpio[109] gpio[109] npc mdo[10] ? h2 v ss_hv_io_ring ? h3 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] h4 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] h6 v dd_lv ? h7 v ss_lv ? h8 v ss_lv ? h9 v ss_lv ? h10 v ss_lv ? h11 v ss_lv ? h12 v dd_lv ? h14 v ss_lv ? h15 v dd_hv_reg_1 ? h16 v dd_hv_fla ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 63/160 h17 h[6] siul gpio[118] gpio[118] flexpwm_1 b[0] b[0] dspi_0 cs5 ? j1 f[7] siul gpio[87] gpio[87] npc mcko ? j2 g[15] siul gpio[111] gpio[111] npc mdo[8] ? j3 v dd_hv_reg_0 ? j4 v dd_hv_reg_0 ? j6 v dd_lv ? j7 v ss_lv ? j8 v ss_lv ? j9 v ss_lv ? j10 v ss_lv ? j11 v ss_lv ? j12 v dd_lv ? j14 v dd_lv ? j15 v dd_hv_reg_1 ? j16 v ss_hv_fla ? j17 h[15] siul gpio[127] gpio[127] flexpwm_1 b[3] b[3] etimer_2 etc[5] etc[5] k1 f[9] siul gpio[89] gpio[89] npc mseo[0] ? k2 f[8] siul gpio[88] gpio[88] npc mseo[1] ? k3 rdy npc rdy ? siul gpio[132] gpio[132] k4 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin k6 v dd_lv ? k7 v ss_lv ? k8 v ss_lv ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 64/160 doc id 15457 rev 8 k9 v ss_lv ? k10 v ss_lv ? k11 v ss_lv ? k12 v dd_lv ? k14 not connected ? k15 h[8] siul gpio[120] gpio[120] flexpwm_1 a[1] a[1] dspi_0 cs6 ? k16 h[7] siul gpio[119] gpio[119] flexpwm_1 x[1] x[1] etimer_2 etc[1] etc[1] k17 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] l1 f[10] siul gpio[90] gpio[90] npc evto ? l2 f[11] siul gpio[91] gpio[91] npc ? evti l3 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? l4 not connected ? l6 v dd_lv ? l7 v ss_lv ? l8 v ss_lv ? l9 v ss_lv ? l10 v ss_lv ? l11 v ss_lv ? l12 v dd_lv ? l14 not connected ? l15 tck ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 65/160 l16 h[4] siul gpio[116] gpio[116] flexpwm_1 x[0] x[0] etimer_2 etc[0] etc[0] l17 b[4] siul gpio[20] gpio[20] jtagc tdo ? m1 v dd_hv_osc ? m2 v dd_hv_io_ring ? m3 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] m4 not connected ? m6 v dd_lv ? m7 v dd_lv ? m8 v dd_lv ? m9 v dd_lv ? m10 v dd_lv ? m11 v dd_lv ? m12 v dd_lv ? m14 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? m15 b[5] siul gpio[21] gpio[21] jtagc ? tdi m16 tms ? m17 h[5] siul gpio[117] gpio[117] flexpwm_1 a[0] a[0] dspi_0 cs4 ? n1 xtal ? n2 v ss_hv_io_ring ? n3 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] n4 v ss_lv_pll0_pll1 ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 66/160 doc id 15457 rev 8 n14 not connected ? n15 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? n16 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] n17 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? p1 v ss_hv_osc ? p2 reset ? p3 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] p4 v dd_lv_pll0_pll1 ? p5 v dd_lv_core_ring ? p6 v ss_lv_core_ring ? p7 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] p8 not connected ? p9 v ss_hv_io_ring ? p10 v dd_hv_io_ring ? p11 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] p12 v dd_lv_core_ring ? p13 v ss_lv_core_ring ? p14 v dd_hv_io_ring ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 67/160 p15 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] p16 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] p17 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] r1 extal ? r2 fccu_f[0] fccu f[0] f[0] r3 v ss_hv_io_ring ? r4 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? r5 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] r6 e[6] siul ? gpio[70] adc_0 ? an[4] r7 v dd_hv_adr0 ? r8 b[10] siul ? gpio[26] adc_0 adc_1 ?an[12] r9 v dd_hv_adr1 ? r10 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] r11 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 68/160 doc id 15457 rev 8 r12 c[0] siul ? gpio[32] adc_1 ? an[3] r13 bctrl ? r14 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] r15 v ss_hv_io_ring ? r16 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] r17 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] t1 v ss_hv_io_ring ? t2 v dd_hv_io_ring ? t3 not connected ? t4 c[1] siul ? gpio[33] adc_0 ? an[2] t5 e[5] siul ? gpio[69] adc_0 ? an[8] t6 e[7] siul ? gpio[71] adc_0 ? an[6] t7 v ss_hv_adr0 ? t8 b[11] siul ? gpio[27] adc_0 adc_1 ?an[13] t9 v ss_hv_adr1 ? t10 e[9] siul ? gpio[73] adc_1 ? an[7] t11 e[10] siul ? gpio[74] adc_1 ? an[8] table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 69/160 t12 e[12] siul ? gpio[76] adc_1 ? an[6] t13 e[0] siul ? gpio[64] adc_1 ? an[5] t14 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] t15 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] t16 v dd_hv_io_ring ? t17 v ss_hv_io_ring ? u1 v ss_hv_io_ring ? u2 v ss_hv_io_ring ? u3 not connected ? u4 e[4] siul ? gpio[68] adc_0 ? an[7] u5 c[2] siul ? gpio[34] adc_0 ? an[3] u6 e[2] siul ? gpio[66] adc_0 ? an[5] u7 b[9] siul ? gpio[25] adc_0 adc_1 ?an[11] u8 b[12] siul ? gpio[28] adc_0 adc_1 ?an[14] u9 v dd_hv_adv ? u10 v ss_hv_adv ? u11 e[11] siul ? gpio[75] adc_1 ? an[4] u12 not connected ? u13 not connected ? u14 v dd_hv_pmu ? table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions spc56xl60/54 70/160 doc id 15457 rev 8 2.2 supply pins u15 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] u16 v ss_hv_io_ring ? u17 v ss_hv_io_ring ? 1. v pp_test should always be tied to ground (v ss ) for normal operations. table 5. lfbga257 pin f unction summary (continued) pin # port/function peripheral ou tput function input function table 6. supply pins supply pin # symbol description 100 pkg 144 pkg 257 pkg vreg control and power supply pins bctrl voltage regulator external npn ballast base control pin 47 69 r13 v dd_lv_cor core logic supply 48 70 vdd_lv (1) v ss_lv_cor core regulator ground 49 71 vss_lv (2) v dd_hv_pmu voltage regulator supply 50 72 u14 adc_0/adc_1 reference voltage and adc supply v dd_hv_adr0 adc_0 high reference voltage 33 50 r7 v ss_hv_adr0 adc_0 low reference voltage 34 51 t7 v dd_hv_adr1 adc_1 high reference voltage 39 56 r9 v ss_hv_adr1 adc_1 low reference voltage 40 57 t9 v dd_hv_adv adc voltage supply for adc_0 and adc_1 41 58 u9 v ss_hv_adv adc ground for adc_0 and adc_1 42 59 u10 power supply pins (3.3 v) v dd_hv_io 3.3 v input/output supply voltage ? 6 vdd_hv (3) v ss_hv_io 3.3 v input/output ground ? 7 vss_hv (4) v dd_hv_reg_0 vdd_hv_reg_0 10 16 j3 v dd_hv_io 3.3 v input/output supply voltage 13 21 vdd_hv (3) v ss_hv_io 3.3 v input/output ground 14 22 vss_hv (4) v dd_hv_osc crystal oscillator amplifier supply voltage 16 27 m1 v ss_hv_osc crystal oscillator amplifier ground 17 28 p1 v ss_hv_io 3.3 v input/output ground 62 90 vss_hv (4) v dd_hv_io 3.3 v input/output supply voltage 63 91 vdd_hv (3)
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 71/160 v dd_hv_reg_1 vdd_hv_reg_1 67 95 h15 v ss_hv_fla vss_hv_fla 68 96 j16 v dd_hv_fla vdd_hv_fla 69 97 h16 v dd_hv_io vdd_hv_io 87 126 vdd_hv (3) v ss_hv_io vss_hv_io 88 127 vss_hv (4) v dd_hv_reg_2 vdd_hv_reg_2 91 130 c7 power supply pins (1.2 v) v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 11 17 vss_hv (2) v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 12 18 vdd_lv (1) v ss 1v2 vss_lv_pll0_pll1 / 1.2 v decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v dd_lv_pll. 24 35 n4 v dd 1v2 vdd_lv_pll0_pll1 decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v ss_lv_pll. 25 36 p4 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 28 39 vdd_lv (1) v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 29 40 vss_lv (2) v dd_lv_cor vdd_lv_cor decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v ss_lv_regcor. ? 70 vdd_lv (1) v ss_lv_cor vss_lv_regcor0 decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v dd_lv_regcor. ? 71 vss_lv (2) v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 65 93 vdd_lv (1) v ss_lv_cor vss_lv_cor / 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 66 94 vss_lv (2) v dd 1v2 vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 92 131 vdd_lv (1) table 6. supply pins (continued) supply pin # symbol description 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 72/160 doc id 15457 rev 8 2.3 system pins v ss 1v2 vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 93 132 vss_lv (2) v dd 1v2 vdd_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. ? 135 vdd_lv (1) v ss 1v2 vss_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. ? 137 vss_lv (2) 1. vdd_lv balls are tied togethe r on the lfbga257 substrate. 2. vss_lv balls are tied together on the lfbga257 substrate. 3. vdd_hv balls are tied together on the lfbga257 substrate. 4. vss_hv balls are tied together on the lfbga257 substrate. table 6. supply pins (continued) supply pin # symbol description 100 pkg 144 pkg 257 pkg table 7. system pins symbol description direction pin # 100 pkg 144 pkg 257 pkg dedicated pins mdo0 (1) nexus message data output ? line output only ? 9 e1 nmi (2) non maskable interrupt input only 1 1 e4 xtal input for oscillator amplifier circuit and internal clock generator input only 18 29 n1 extal (3) oscillator amplifier output input/output (4) 19 30 r1 tms (2) jtag state machine control input only 59 87 m16 tck (2) jtag clock input only 60 88 l15 jcomp (5) jtag compliance select input only 84 123 c10 reset pin reset bidirectional reset with schmit t-trigger characteristics and noise filter. this pin has medium drive strength. output drive is open drain and must be terminated by an external resistor of value 1kohm. (6) bidirectional 20 31 p2 test pin vpp test pin for testing purpose only. to be tied to ground in normal operating mode. 74 107 d15 1. this pad is configured for fast (f) pad speed.
spc56xl60/54 package pinout s and signal descriptions doc id 15457 rev 8 73/160 note: none of system pins (except r eset) provides an open drain output. 2.4 pin muxing ta bl e 8 defines the pin list and muxing for this device. each entry of ta b l e 8 shows all the possible configurations for each pin, via the alternate functions. the default function assigned to each pin after reset is indicated by alt0. note: pins labeled ?nc? are to be left unconnected. any connection to an external circuit or voltage may cause unpredictable device behavior or damage. pins labeled ?reserved? are to be tied to ground. not doing so may cause unpredictable device behavior. 2. this pad contains a weak pull-up. 3. extal is an "output" in "crystal" mode, and is an "input" in "ext clock" mode. 4. in xosc bypass mode, the analog portion of crystal oscillator (amplifier) is disabl ed. an external clock can be applied at extal as an input. in xosc normal mode, extal is an output 5. this pad contains a weak pull-down. 6. reset output shall be considered valid only a fter the 3.3v supply reaches its stable value.
package pinouts and signal descriptions spc56xl60/54 74/160 doc id 15457 rev 8 table 8. pin muxing port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg port a a[0] pcr[0] siul gpio[0] alt0 gpio[0] ? ?ms5173t14 etimer_0 etc[0] alt1 etc[0] psmi[35]; padsel=0 dspi_2 sck alt2 sck psmi[1]; padsel=0 siul ? ? eirq[0] ? a[1] pcr[1] siul gpio[1] alt0 gpio[1] ? ?ms5274r14 etimer_0 etc[1] alt1 etc[1] psmi[36]; padsel=0 dspi_2 sout alt2 ? ? siul ? ? eirq[1] ? a[2] pcr[2] siul gpio[2] alt0 gpio[2] ? pull down m s 57 84 n16 etimer_0 etc[2] alt1 etc[2] psmi[37]; padsel=0 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=0 dspi_2 ? ? sin psmi[2]; padsel=0 mc_rgm ? ? abs[0] ? siul ? ? eirq[2] ?
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 75/160 a[3] pcr[3] siul gpio[3] alt0 gpio[3] ? pull down m s 64 92 k17 etimer_0 etc[3] alt1 etc[3] psmi[38]; padsel=0 dspi_2 cs0 alt2 cs0 psmi[3]; padsel=0 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=0 mc_rgm ? ? abs[2] ? siul ? ? eirq[3] ? a[4] pcr[4] siul gpio[4] alt0 gpio[4] ? pull down m s 75 108 c16 etimer_1 etc[0] alt1 etc[0] psmi[9]; padsel=0 dspi_2 cs1 alt2 ? ? etimer_0 etc[4] alt3 etc[4] psmi[7]; padsel=0 mc_rgm ? ? fab ? siul ? ? eirq[4] ? a[5] pcr[5] siul gpio[5] alt0 gpio[5] ? ?ms814h4 dspi_1 cs0 alt1 cs0 ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=0 dspi_0 cs7 alt3 ? ? siul ? ? eirq[5] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 76/160 doc id 15457 rev 8 a[6] pcr[6] siul gpio[6] alt0 gpio[6] ? ?ms22g4 dspi_1 sck alt1 sck ? siul ? ? eirq[6] ? a[7] pcr[7] siul gpio[7] alt0 gpio[7] ? ?ms410f3 dspi_1 sout alt1 ? ? siul ? ? eirq[7] ? a[8] pcr[8] siul gpio[8] alt0 gpio[8] ? ?ms612f4 dspi_1 ? ? sin ? siul ? ? eirq[8] ? a[9] pcr[9] siul gpio[9] alt0 gpio[9] ? ?ms94134b6 dspi_2 cs1 alt1 ? ? flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=0 a[10] pcr[10] siul gpio[10] alt0 gpio[10] ? ?ms81118a13 dspi_2 cs0 alt1 cs0 psmi[3]; padsel=1 flexpwm_0 b[0] alt2 b[0] psmi[24]; padsel=0 flexpwm_0 x[2] alt3 x[2] psmi[29]; padsel=0 siul ? ? eirq[9] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 77/160 a[11] pcr[11] siul gpio[11] alt0 gpio[11] ? ?ms82120d11 dspi_2 sck alt1 sck psmi[1]; padsel=1 flexpwm_0 a[0] alt2 a[0] psmi[20]; padsel=0 flexpwm_0 a[2] alt3 a[2] psmi[22]; padsel=0 siul ? ? eirq[10] ? a[12] pcr[12] siul gpio[12] alt0 gpio[12] ? ?ms83122a10 dspi_2 sout alt1 ? ? flexpwm_0 a[2] alt2 a[2] psmi[22]; padsel=1 flexpwm_0 b[2] alt3 b[2] psmi[26]; padsel=0 siul ? ? eirq[11] ? a[13] pcr[13] siul gpio[13] alt0 gpio[13] ? ?ms95136c6 flexpwm_0 b[2] alt2 b[2] psmi[26]; padsel=1 dspi_2 ? ? sin psmi[2]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=1 siul ? ? eirq[12] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 78/160 doc id 15457 rev 8 a[14] pcr[14] siul gpio[14] alt0 gpio[14] ? ?ms99143b4 flexcan_1 txd alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=0 siul ? ? eirq[13] ? a[15] pcr[15] siul gpio[15] alt0 gpio[15] ? ?ms100144d3 etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=0 flexcan_0 ? ? rxd psmi[33]; padsel=0 siul ? ? eirq[14] ? port b b[0] pcr[16] siul gpio[16] alt0 gpio[16] ? ?ms76109b15 flexcan_0 txd alt1 ? ? etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=0 sscm debug[0] alt3 ? ? siul ? ? eirq[15] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 79/160 b[1] pcr[17] siul gpio[17] alt0 gpio[17] ? ?ms77110c14 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=0 sscm debug[1] alt3 ? ? flexcan_0 ? ? rxd psmi[33]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=1 siul ? ? eirq[16] ? b[2] pcr[18] siul gpio[18] alt0 gpio[18] ? ?ms79114a14 linflexd_0 txd alt1 ? ? sscm debug[2] alt3 ? ? siul ? ? eirq[17] ? b[3] pcr[19] siul gpio[19] alt0 gpio[19] ? ?ms80116b13 sscm debug[3] alt3 ? ? linflexd_0 ? ? rxd psmi[31]; padsel=0 b[4] (2) pcr[20] siul gpio[20] alt0 gpio[20] ? ? f s 61 89 l17 jtagc tdo alt1 ? ? b[5] pcr[21] siul gpio[21] alt0 gpio[21] ? pull up m s 58 86 m15 jtagc ? ? tdi ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 80/160 doc id 15457 rev 8 b[6] pcr[22] siul gpio[22] alt0 gpio[22] ? ?fs96138b3 mc_cgm clk_out alt1 ? ? dspi_2 cs2 alt2 ? ? siul ? eirq[18] ? b[7] pcr[23] siul ? alt0 gpi[23] ? ???3043r5 linflexd_0 ? ? rxd psmi[31]; padsel=1 adc_0 ? ? an[0] (3) ? b[8] pcr[24] siul ? alt0 gpi[24] ? ???3147p7 etimer_0 ? ? etc[5] psmi[8]; padsel=2 adc_0 ? ? an[1] (3) ? b[9] pcr[25] siul ? alt0 gpi[25] ? ???3552u7 adc_0 adc_1 ??an[11] (3) ? b[10] pcr[26] siul ? alt0 gpi[26] ? ???3653r8 adc_0 adc_1 ??an[12] (3) ? b[11] pcr[27] siul ? alt0 gpi[27] ? ???3754t8 adc_0 adc_1 ??an[13] (3) ? b[12] pcr[28] siul ? alt0 gpi[28] ? ???3855u8 adc_0 adc_1 ??an[14] (3) ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 81/160 b[13] pcr[29] siul ? alt0 gpi[29] ? ???4360r10 linflexd_1 ? ? rxd psmi[32]; padsel=0 adc_1 ? ? an[0] (3) ? b[14] pcr[30] siul ? alt0 gpi[30] ? ???4464p11 etimer_0 ? ? etc[4] psmi[7]; padsel=2 siul ? ? eirq[19] ? adc_1 ? ? an[1] (3) ? b[15] pcr[31] siul ? alt0 gpi[31] ? ????62r11 siul ? ? eirq[20] ? adc_1 ? ? an[2] (3) ? port c c[0] pcr[32] siul ? alt0 gpi[32] ? ???4566r12 adc_1 ? ? an[3] (3) ? c[1] pcr[33] siul ? alt0 gpi[33] ? ????41t4 adc_0 ? ? an[2] (3) ? c[2] pcr[34] siul ? alt0 gpi[34] ? ????45u5 adc_0 ? ? an[3] (3) ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 82/160 doc id 15457 rev 8 c[4] pcr[36] siul gpio[36] alt0 gpio[36] ? ?ms511h3 dspi_0 cs0 alt1 cs0 ? flexpwm_0 x[1] alt2 x[1] psmi[28]; padsel=0 sscm debug[4] alt3 ? ? siul ? ? eirq[22] ? c[5] pcr[37] siul gpio[37] alt0 gpio[37] ? ?ms713g3 dspi_0 sck alt1 sck ? sscm debug[5] alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=0 siul ? ? eirq[23] ? c[6] pcr[38] siul gpio[38] alt0 gpio[38] ? ?ms98142d4 dspi_0 sout alt1 ? ? flexpwm_0 b[1] alt2 b[1] psmi[25]; padsel=0 sscm debug[6] alt3 ? ? siul ? ? eirq[24] ? c[7] pcr[39] siul gpio[39] alt0 gpio[39] ? ?ms915k4 flexpwm_0 a[1] alt2 a[1] psmi[21]; padsel=0 sscm debug[7] alt3 ? ? dspi_0 ? ? sin ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 83/160 c[10] pcr[42] siul gpio[42] alt0 gpio[42] ? ?ms78111a15 dspi_2 cs2 alt1 ? ? flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=0 c[11] pcr[43] siul gpio[43] alt0 gpio[43] ? ?ms5580m14 etimer_0 etc[4] alt1 etc[4] psmi[7]; padsel=1 dspi_2 cs2 alt2 ? ? c[12] pcr[44] siul gpio[44] alt0 gpio[44] ? ?ms5682n15 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=0 dspi_2 cs3 alt2 ? ? c[13] pcr[45] siul gpio[45] alt0 gpio[45] ? ?ms71101f15 etimer_1 etc[1] alt1 etc[1] psmi[10]; padsel=0 ctu_0 ? ? ext_in psmi[0]; padsel=0 flexpwm_0 ? ? ext_sync psmi[15]; padsel=0 c[14] pcr[46] siul gpio[46] alt0 gpio[46] ? ?ms72103e15 etimer_1 etc[2] alt1 etc[2] psmi[11]; padsel=1 ctu_0 ext_tgr alt2 ? ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 84/160 doc id 15457 rev 8 c[15] pcr[47] siul gpio[47] alt0 gpio[47] ? ? sym s 85 124 a8 flexray ca_tr_en alt1 ? ? etimer_1 etc[0] alt2 etc[0] psmi[9]; padsel=1 flexpwm_0 a[1] alt3 a[1] psmi[21]; padsel=1 ctu_0 ? ? ext_in psmi[0]; padsel=1 flexpwm_0 ? ? ext_sync psmi[15]; padsel=1 port d d[0] pcr[48] siul gpio[48] alt0 gpio[48] ? ? sym s 86 125 b8 flexray ca_tx alt1 ? ? etimer_1 etc[1] alt2 etc[1] psmi[10]; padsel=1 flexpwm_0 b[1] alt3 b[1] psmi[25]; padsel=1 d[1] pcr[49] siul gpio[49] alt0 gpio[49] ? ?ms33e3 etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=2 ctu_0 ext_tgr alt3 ? ? flexray ? ? ca_rx ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 85/160 d[2] pcr[50] siul gpio[50] alt0 gpio[50] ? ?ms?140c5 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=1 flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=0 flexray ? ? cb_rx ? d[3] pcr[51] siul gpio[51] alt0 gpio[51] ? ? sym s 89 128 a7 flexray cb_tx alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=1 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=2 d[4] pcr[52] siul gpio[52] alt0 gpio[52] ? ? sym s 90 129 b7 flexray cb_tr_en alt1 ? ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=2 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=2 d[5] pcr[53] siul gpio[53] alt0 gpio[53] ? ?ms2233n3 dspi_0 cs3 alt1 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=0 table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 86/160 doc id 15457 rev 8 d[6] pcr[54] siul gpio[54] alt0 gpio[54] ? ?ms2334p3 dspi_0 cs2 alt1 ? ? flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=1 d[7] pcr[55] siul gpio[55] alt0 gpio[55] ? ?ms2637r4 dspi_1 cs3 alt1 ? ? dspi_0 cs4 alt3 ? ? swg analog output ? ? ? d[8] pcr[56] siul gpio[56] alt0 gpio[56] ? ?ms2132m3 dspi_1 cs2 alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=2 dspi_0 cs5 alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=1 d[9] pcr[57] siul gpio[57] alt0 gpio[57] ? ? m s 1526l3 flexpwm_0 x[0] alt1 x[0] ? linflexd_1 txd alt2 ? ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 87/160 d[10] pcr[58] siul gpio[58] alt0 gpio[58] ? ?ms5376t15 flexpwm_0 a[0] alt1 a[0] psmi[20]; padsel=1 etimer_0 ? ? etc[0] psmi[35]; padsel=1 d[11] pcr[59] siul gpio[59] alt0 gpio[59] ? ?ms5478r16 flexpwm_0 b[0] alt1 b[0] psmi[24]; padsel=1 etimer_0 ? ? etc[1] psmi[36]; padsel=1 d[12] pcr[60] siul gpio[60] alt0 gpio[60] ?ms7099g14 flexpwm_0 x[1] alt1 x[1] psmi[28]; padsel=1 linflexd_1 ? ? rxd psmi[32]; padsel=1 d[14] pcr[62] siul gpio[62] alt0 gpio[62] ? ?ms73105d16 flexpwm_0 b[1] alt1 b[1] psmi[25]; padsel=2 etimer_0 ? ? etc[3] psmi[38]; padsel=1 port e e[0] pcr[64] siul ? alt0 gpi[64] ? ???4668t13 adc_1 ? ? an[5] (3) ? e[2] pcr[66] siul ? alt0 gpi[66] ? ???3249u6 adc_0 ? ? an[5] (3) ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 88/160 doc id 15457 rev 8 e[4] pcr[68] siul ? alt0 gpi[68] ? ????42u4 adc_0 ? ? an[7] (3) ? e[5] pcr[69] siul ? alt0 gpi[69] ? ????44t5 adc_0 ? ? an[8] (3) ? e[6] pcr[70] siul ? alt0 gpi[70] ? ????46r6 adc_0 ? ? an[4] (3) ? e[7] pcr[71] siul ? alt0 gpi[71] ? ????48t6 adc_0 ? ? an[6] (3) ? e[9] pcr[73] siul ? alt0 gpi[73] ? ????61t10 adc_1 ? ? an[7] (3) ? e[10] pcr[74] siul ? alt0 gpi[74] ? ????63t11 adc_1 ? ? an[8] (3) ? e[11] pcr[75] siul ? alt0 gpi[75] ? ????65u11 adc_1 ? ? an[4] (3) ? e[12] pcr[76] siul ? alt0 gpi[76] ? ????67t12 adc_1 ? ? an[6] (3) ? e[13] pcr[77] siul gpio[77] alt0 gpio[77] ? ? m s ? 117 d12 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=1 dspi_2 cs3 alt2 ? ? siul ? ? eirq[25] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 89/160 e[14] pcr[78] siul gpio[78] alt0 gpio[78] ? ?ms?119b12 etimer_1 etc[5] alt1 etc[5] psmi[14]; padsel=3 siul ? ? eirq[26] ? e[15] pcr[79] siul gpio[79] alt0 gpio[79] ? ?ms?121b11 dspi_0 cs1 alt1 ? ? siul ? ? eirq[27] ? port f f[0] pcr[80] siul gpio[80] alt0 gpio[80] ? ?ms?133d7 flexpwm_0 a[1] alt1 a[1] psmi[21]; padsel=2 etimer_0 ? ? etc[2] psmi[37]; padsel=1 siul ? ? eirq[28] ? f[3] pcr[83] siul gpio[83] alt0 gpio[83] ? ?ms?139b5 dspi_0 cs6 alt1 ? ? f[4] pcr[84] siul gpio[84] alt0 gpio[84] ? ?fs?4d2 npc mdo[3] alt2 ? ? f[5] pcr[85] siul gpio[85] alt0 gpio[85] ? ?fs?5d1 npc mdo[2] alt2 ? ? f[6] pcr[86] siul gpio[86] alt0 gpio[86] ? ?fs?8e2 npc mdo[1] alt2 ? ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 90/160 doc id 15457 rev 8 f[7] pcr[87] siul gpio[87] alt0 gpio[87] ? ?fs?19j1 npc mcko alt2 ? ? f[8] pcr[88] siul gpio[88] alt0 gpio[88] ? ?fs?20k2 npc mseo[1] alt2 ? ? f[9] pcr[89] siul gpio[89] alt0 gpio[89] ? ?fs?23k1 npc mseo[0] alt2 ? ? f[10] pcr[90] siul gpio[90] alt0 gpio[90] ? ?fs?24l1 npc evto alt2 ? ? f[11] pcr[91] siul gpio[91] alt0 gpio[91] ? ?ms?25l2 npc ? alt2 evti ? f[12] pcr[92] siul gpio[92] alt0 gpio[92] ? ? m s ? 106 c17 etimer_1 etc[3] alt1 etc[3] psmi[12]; padsel=2 siul ? ? eirq[30] ? f[13] pcr[93] siul gpio[93] alt0 gpio[93] ? ?ms?112b14 etimer_1 etc[4] alt1 etc[4] psmi[13]; padsel=3 siul ? ? eirq[31] ? f[14] pcr[94] siul gpio[94] alt0 gpio[94] ? ? m s ? 115 c13 linflexd_1 txd alt1 ? ? f[15] pcr[95] siul gpio[95] alt0 gpio[95] ? ? m s ? 113 d13 linflexd_1 ? ? rxd psmi[32]; padsel=2 table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 91/160 fccu fccu_ f[0] ? fccu f[0] alt0 f[0] ? ? s s 27 38 r2 fccu_ f[1] ? fccu f[1] alt0 f[1] ? ? s s 97 141 c4 port g g[2] pcr[98] siul gpio[98] alt0 gpio[98] ? ?ms?102e16 flexpwm_0 x[2] alt1 x[2] psmi[29]; padsel=1 dspi_1 cs1 alt2 ? ? g[3] pcr[99] siul gpio[99] alt0 gpio[99] ? ? m s ? 104 d17 flexpwm_0 a[2] alt1 a[2] psmi[22]; padsel=2 etimer_0 ? ? etc[4] psmi[7]; padsel=3 g[4] pcr[100] siul gpio[100] alt0 gpio[100] ? ?ms?100f17 flexpwm_0 b[2] alt1 b[2] psmi[26]; padsel=2 etimer_0 ? ? etc[5] psmi[8]; padsel=3 g[5] pcr[101] siul gpio[101] alt0 gpio[101] ? ?ms?85n17 flexpwm_0 x[3] alt1 x[3] psmi[30]; padsel=2 dspi_2 cs3 alt2 ? ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 92/160 doc id 15457 rev 8 g[6] pcr[102] siul gpio[102] alt0 gpio[102] ? ?ms?98g17 flexpwm_0 a[3] alt1 a[3] psmi[23]; padsel=3 g[7] pcr[103] siul gpio[103] alt0 gpio[103] ?ms?83p17 flexpwm_0 b[3] alt1 b[3] psmi[27]; padsel=3 g[8] pcr[104] siul gpio[104] alt0 gpio[104] ? ?ms?81p16 flexray dbg0 alt1 ? ? dspi_0 cs1 alt2 ? ? flexpwm_0 ? ? fault[0] psmi[16]; padsel=2 siul ? ? eirq[21] ? g[9] pcr[105] siul gpio[105] alt0 gpio[105] ? ?ms?79r17 flexray dbg1 alt1 ? ? dspi_1 cs1 alt2 ? ? flexpwm_0 ? ? fault[1] psmi[17]; padsel=2 siul ? ? eirq[29] ? g[10] pcr[106] siul gpio[106] alt0 gpio[106] ? ?ms?77p15 flexray dbg2 alt1 ? ? dspi_2 cs3 alt2 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=1 table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 93/160 g[11] pcr[107] siul gpio[107] alt0 gpio[107] ? ?ms?75u15 flexray dbg3 alt1 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=2 g[12] pcr[108] siul gpio[108] alt0 gpio[108] ? ?fs??f2 npc mdo[11] alt2 ? ? g[13] pcr[109] siul gpio[109] alt0 gpio[109] ? ?fs??h1 npc mdo[10] alt2 ? ? g[14] pcr[110] siul gpio[110] alt0 gpio[110] ? ?fs??a6 npc mdo[9] alt2 ? ? g[15] pcr[111] siul gpio[111] alt0 gpio[111] ? ?fs??j2 npc mdo[8] alt2 ? ? port h h[0] pcr[112] siul gpio[112] alt0 gpio[112] ? ?fs??a5 npc mdo[7] alt2 ? ? h[1] pcr[113] siul gpio[113] alt0 gpio[113] ? ?fs??f1 npc mdo[6] alt2 ? ? h[2] pcr[114] siul gpio[114] alt0 gpio[114] ? ?fs??a4 npc mdo[5] alt2 ? ? h[3] pcr[115] siul gpio[115] alt0 gpio[115] ? ?fs??g1 npc mdo[4] alt2 ? ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 94/160 doc id 15457 rev 8 h[4] pcr[116] siul gpio[116] alt0 gpio[116] ? ? m s ? ? l16 flexpwm_1 x[0] alt1 x[0] ? etimer_2 etc[0] alt2 etc[0] psmi[39]; padsel=0 h[5] pcr[117] siul gpio[117] alt0 gpio[117] ? ?ms??m17 flexpwm_1 a[0] alt1 a[0] ? dspi_0 cs4 alt3 ? ? h[6] pcr[118] siul gpio[118] alt0 gpio[118] ? ?ms??h17 flexpwm_1 b[0] alt1 b[0] ? dspi_0 cs5 alt3 ? ? h[7] pcr[119] siul gpio[119] alt0 gpio[119] ? ?ms??k16 flexpwm_1 x[1] alt1 x[1] ? etimer_2 etc[1] alt2 etc[1] psmi[40]; padsel=0 h[8] pcr[120] siul gpio[120] alt0 gpio[120] ? ?ms??k15 flexpwm_1 a[1] alt1 a[1] ? dspi_0 cs6 alt3 ? ? h[9] pcr[121] siul gpio[121] alt0 gpio[121] ? ?ms??g16 flexpwm_1 b[1] alt1 b[1] ? dspi_0 cs7 alt3 ? ? h[10] pcr[122] siul gpio[122] alt0 gpio[122] ? ?ms??a11 flexpwm_1 x[2] alt1 x[2] ? etimer_2 etc[2] alt2 etc[2] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 package pinouts and signal descriptions doc id 15457 rev 8 95/160 h[11] pcr[123] siul gpio[123] alt0 gpio[123] ? ?ms??c11 flexpwm_1 a[2] alt1 a[2] ? h[12] pcr[124] siul gpio[124] alt0 gpio[124] ? ?ms??b10 flexpwm_1 b[2] alt1 b[2] ? h[13] pcr[125] siul gpio[125] alt0 gpio[125] ? ?ms??g15 flexpwm_1 x[3] alt1 x[3] ? etimer_2 etc[3] alt2 etc[3] psmi[42]; padsel=0 h[14] pcr[126] siul gpio[126] alt0 gpio[126] ? ?ms??a12 flexpwm_1 a[3] alt1 a[3] ? etimer_2 etc[4] alt2 etc[4] ? h[15] pcr[127] siul gpio[127] alt0 gpio[127] ? ?ms??j17 flexpwm_1 b[3] alt1 b[3] ? etimer_2 etc[5] alt2 etc[5] ? port i i[0] pcr[128] siul gpio[128] alt0 gpio[128] ? ?ms??c9 etimer_2 etc[0] alt1 etc[0] psmi[39]; padsel=1 dspi_0 cs4 alt2 ? ? flexpwm_1 ? ? fault[0] ? table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
package pinouts and signal descriptions spc56xl60/54 96/160 doc id 15457 rev 8 note: open drain can be configured by the pcrn for all pins used as output (excep t fccu_f[0] and fccu_f[1] ). i[1] pcr[129] siul gpio[129] alt0 gpio[129] ? ?ms??c12 etimer_2 etc[1] alt1 etc[1] psmi[40]; padsel=1 dspi_0 cs5 alt2 ? ? flexpwm_1 ? ? fault[1] ? i[2] pcr[130] siul gpio[130] alt0 gpio[130] ? ?ms??f16 etimer_2 etc[2] alt1 etc[2] psmi[41]; padsel=1 dspi_0 cs6 alt2 ? ? flexpwm_1 ? ? fault[2] ? i[3] pcr[131] siul gpio[131] alt0 gpio[131] ? ?ms??e17 etimer_2 etc[3] alt1 etc[3] psmi[42]; padsel=1 dspi_0 cs7 alt2 ? ? ctu_0 ext_tgr alt3 ? ? flexpwm_1 ? ? fault[3] ? rdy pcr[132] siul gpio[132] alt0 gpio[132] ? ?fs?? k3 npc rdy alt2 ? ? 1. programmable via the src (slew rate control) bit in the respec tive pad configuration register ; s = slow, m = medium, f = fast, sym = symmetric (for flexray) 2. the default function of this pin out of reset is alt1 (tdo). 3. analog table 8. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed (1) pin # src =1 src =0 100 pkg 144 pkg 257 pkg
spc56xl60/54 electrical characteristics doc id 15457 rev 8 97/160 3 electrical characteristics 3.1 introduction this section contains detaile d information on power considerations, dc/ac electrical characteristics, and ac timing specifications for this device. this device is designed to operate at 120 mhz . the electrical specifications are preliminary and are from previous designs, design simulations , or initial evaluation. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterizati on and device qualifications have been completed. the ?symbol? column of the electrical parameter and timings tables contains an additional column containing ?sr?, ?cc?, ?p?, ?c?, ?t?, or ?d?. ?sr? identifies system requirements?conditions that must be provided to ensure normal device operation. an example is the input voltage of a voltage regulator. ?cc? identifies controller characteristics?indicating the characteristics and timing of the signals that the chip provides. ?p?, ?c?, ?t?, or ?d? apply only to controller characteristics?specifications that define normal device operation. they specify how each characteristic is guaranteed. ? p: parameter is guaranteed by production testing of each individual device. ? c: parameter is guaranteed by design characterization. measurements are taken from a statistically relevant sample size across process variations. ? t: parameter is guaranteed by design characterization on a small sample size from typical devices under typical condit ions unless otherwise noted. all values are shown in the typical (?typ?) column are within this category. ? d: parameters are derived mainly from simulations. 3.2 absolute maximum ratings table 9. absolute maximum ratings (1) symbol parameter conditions min max (2) unit v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? ?0.3 4.0 (3), (4) v v dd_hv_iox sr 3.3 v input/output supply voltage ? ?0.3 4.0 (3), (4) v v ss_hv_iox sr input/output ground voltage ? ?0.1 0.1 v v dd_hv_fla sr 3.3 v flash supply voltage ? ?0.3 4.0 (3), (4) v v ss_hv_fla sr flash memory ground ? ?0.1 0.1 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ? ?0.3 4.0 (3), (4) v v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ? ?0.1 0.1 v v dd_hv_adr0 (5) v dd_hv_adr1 sr 3.3 v / 5.0 v adc_0 high reference voltage 3.3 v / 5.0 v adc_1 high reference voltage ? ?0.3 6.0 v
electrical characteristics spc56xl60/54 98/160 doc id 15457 rev 8 3.3 recommended operating conditions v ss_hv_adr0 v ss_hv_adr1 sr adc_0 ground and low reference voltage adc_1 ground and low reference voltage ? ?0.1 0.1 v v dd_hv_adv sr 3.3 v adc supply voltage ? ?0.3 4.0 (3), (4) v v ss_hv_adv sr 3.3 v adc supply ground ? ?0.1 0.1 v tv dd sr supply ramp rate ? 3.0 10 -6 (3.0 v/sec) 0.5 v/s v/s v in sr voltage on any pin with respect to ground (v ss_hv_io x ) ? ?0.3 6.0 (6) v relative to v dd ?0.3 v dd +0.3 (6), (7) i injpad sr injected input current on any pin during overload condition ? ?10 10 ma i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 ma t stg sr storage temperature ? ?55 150 c 1. functional operating conditions are given in the dc electrical characteristics. abso lute maximum ratings are stress ratings only, and functional operation at the maxima is not guarant eed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. absolute maximum voltages are currently maximum burn-in vo ltages. absolute maximum specif ications for device stress have not yet been determined. 3. 5.3 v for 10 hours cumulative over lifetime of device, 3.3 v +10% for time remaining. 4. voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5. v dd_hv_adr0 and v dd_hv_adr1 cannot be operated be operated at different voltages, and need to be supplied by the same voltage source. 6. internal structures hold the input voltage less than the ma ximum voltage on all pads powered by vdde supplies, if the maximum injection current specification is met (2 ma for all pins) and vdde is within the operating voltage specifications. 7. only when v dd < 5.2 v. table 9. absolute maximum ratings (1) (continued) symbol parameter conditions min max (2) unit table 10. recommended operating conditions (3.3 v) symbol parameter conditions min (1) max unit v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? 3.0 3.6 v v dd_hv_iox sr 3.3 v input/output supply voltage ? 3.0 3.6 v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fla sr 3.3 v flash supply voltage ? 3.0 3.6 v v ss_hv_fla sr flash memory ground ? 0 0 v v dd_hv_osc sr 3.3 v crystal oscillator amp lifier supply voltage ? 3.0 3.6 v v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ?00v v dd_hv_adr0 (2) v dd_hv_adr1 sr 3.3 v / 5.0 v adc_0 high reference voltage 3.3 v / 5.0 v adc_1 high reference voltage ? 4.5 to 5.5 or 3.0 to 3.6 v
spc56xl60/54 electrical characteristics doc id 15457 rev 8 99/160 3.4 thermal characteristics v dd_hv_adv sr 3.3 v adc supply voltage ? 3.0 3.6 v v ss_hv_ad0 v ss_hv_ad1 sr adc_0 ground and low reference voltage adc_1 ground and low reference voltage ?00v v ss_hv_adv sr 3.3 v adc supply ground ? 0 0 v v dd_lv_regcor (3) sr internal supply voltage ? ? ? v v ss_lv_regcor (4) sr internal reference voltage ? 0 0 v v dd_lv_cor x (2) sr internal supply voltage ? ? ? v v ss_lv_cor x (3) sr internal reference voltage ? 0 0 v v dd_lv_pll (2) sr internal supply voltage ? ? ? v v ss_lv_pll (3) sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias f cpu 120 mhz ?40 125 c t j sr junction temperature under bias ? ?40 150 c 1. full functionality cannot be guaranteed when voltage drops below 3.0 v. in particula r, adc electrical characteristics and i/os dc electrical specification may not be guaranteed. 2. v dd_hv_adr0 and v dd_hv_adr1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 3. can be connected to emitter of external npn. low voltage supplies are not under user cont rol. they are produced by an on-chip voltage regulator. 4. for the device to function properly, the low voltage grounds (v ss_lv_ xxx ) must be shorted to high voltage grounds (v ss_hv_ xxx ) and the low voltage supply pins (v dd_lv_ xxx ) must be connected to the external ballast emitter, if one is used. table 10. recommended operating conditions (3.3 v) (continued) symbol parameter conditions min (1) max unit table 11. thermal characteristics for lqfp100 package (1) symbol parameter con ditions value unit r ja d thermal resistance, junction-to-ambient natural convection (2) single layer board ? 1s 46 c/w four layer board ? 2s2p 34 r jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 36 c/w four layer board ? 2s2p 28 r jb d thermal resistance junction-to-board (3) ?19c/w r jc d thermal resistance junction-to-case (4) ?8c/w jt d junction-to-package-top natural convection (5) ?2c/w 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power diss ipation of other components on the board, and board thermal resistance. 2. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer.
electrical characteristics spc56xl60/54 100/160 doc id 15457 rev 8 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt. table 12. thermal characteristics for lqfp144 package (1) symbol parameter conditions value unit r ja d thermal resistance, junction-to-ambient natural convection (2) single layer board ? 1s 44 c/w four layer board ? 2s2p 36 r jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 35 c/w four layer board ? 2s2p 30 r jb d thermal resistance junction-to-board (3) ?24c/w r jc d thermal resistance junction-to-case (4) ?8c/w jt d junction-to-package-top natural convection (5) ?2c/w 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power diss ipation of other components on the board, and board thermal resistance. 2. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt. table 13. thermal characteristics for lfbga257 package (1) symbol parameter conditions value unit r ja d thermal resistance junction-to-ambient natural convection (2) single layer board ? 1s 46 c/w four layer board ? 2s2p 26 r jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 37 c/w four layer board ? 2s2p 22 r jb d thermal resistance junction-to-board (3) ?13c/w r jc d thermal resistance junction-to-case (4) ?8c/w jt d junction-to-package-top natural convection (5) ?2c/w 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power diss ipation of other components on the board, and board thermal resistance. 2. junction-to-ambient thermal resist ance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3. junction-to-board thermal re sistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 5. thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the therma l characterization pa rameter is written as psi-jt.
spc56xl60/54 electrical characteristics doc id 15457 rev 8 101/160 3.4.1 general notes for sp ecifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : equation 1 t j =t a +(r ja p d ) where: t a = ambient temperature for the package ( o c) r ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: equation 2 r ja =r jc + r ca where: r ja = junction to ambient thermal resistance (c/w) r jc = junction to case thermal resistance (c/w) r ca = case to ambient thermal resistance (c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using equation 3 : equation 3 t j =t t +( jt p d ) where: t t = thermocouple temperature on top of the package (c) jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
electrical characteristics spc56xl60/54 102/160 doc id 15457 rev 8 references semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 mil-spec and eia/jesd (jedec) specificatio ns are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semitherm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of semitherm, san diego, 1999, pp. 212?220. 3.5 electromagnetic interfer ence (emi) characteristics the characteristics in ta b l e 1 5 were measured using: device configuration, tet conditions, and em testing per standard iec61967-2 supply voltage of 3.3 v dc ambient temperature of 25 c the configuration information referenced in ta bl e 1 5 is explained in ta bl e 1 4 . table 14. emi configuration summary configuration name description configuration a ? high emission = all pads have max slew rate, lvds pads running at 40 mhz ? oscillator frequency = 40 mhz ? system bus frequency = 80 mhz ? no pll frequency modulation ? iec level i ( 36 db v) configuration b ? reference emission = pads use min, mid and max slew rates, lvds pads disabled ? oscillator frequency = 40 mhz ? system bus frequency = 80 mhz ? 2% pll frequency modulation ? iec level k( 30 db v)
spc56xl60/54 electrical characteristics doc id 15457 rev 8 103/160 emc testing was performed and documented according to these standards: [iec61508-2- 7.4.5.1.b, iec61508-2-7.2.3.2.e, iec61508-2-table-a.17 (partially), iec61508-2-table- b.5(partially),srs2110] eme testing was performed and documented according to these standards: [iec 61967-2 & -4] ems testing was performed and documented according to these standards: [iec 62132-2 & -4] contact fsl for detailed information pertaining to the emc, eme, and ems testing and results. 3.6 electrostatic discharg e (esd) characteristics electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts ( n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. for more details, refer to the application note electrostatic discharge sensitivity measurement (an1181). table 15. emi emission testing specifications symbol parameter conditions min typ max unit v eme cc radiated emissions configuration a; frequency range 150 khz?50 mhz ?16? db v configuration a; frequency range 50? 150 mhz ?16? configuration a; frequency range 150? 500 mhz ?32? configuration a; frequency range 500? 1000 mhz ?25? configuration b; frequency range 50? 150 mhz ?15? configuration b; frequency range 50? 150 mhz ?21? configuration b; frequency range 150? 500 mhz ?30? configuration b; frequency range 500? 1000 mhz ?24? table 16. esd ratings (1), (2) no. symbol parameter conditions class max value (3) unit 1v esd(hbm) sr electrostatic discharge (human body model) t a =25c conforming to aec-q100-002 h1c 2000 v 2v esd(mm) sr electrostatic discharge (machine model) t a =25c conforming to aec-q100-003 m2 200 v
electrical characteristics spc56xl60/54 104/160 doc id 15457 rev 8 3.7 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin. a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.8 voltage regulator electrical characteristics the voltage regulator is composed of the following blocks: high power regulator hpreg1 (internal ballast to support core current) high power regulator hpreg2 (external npn to support core current) low voltage detector (lvd_main_1) for 3.3 v supply to io (v ddio ) low voltage detector (lvd_main_2) for 3.3 v supply (v ddreg ) low voltage detector (lvd_main_3) for 3.3 v flash supply (v ddflash ) low voltage detector (lvd_dig_main) for 1.2 v digital core supply (hpv dd ) low voltage detector (lvd_dig_bkup) for the self-test of lvd_dig_main high voltage detector (hvd_dig_main) for 1.2 v digital core supply (hpv dd ) high voltage detector (hvd_dig_bkup) for the self-test of hvd_dig_main. power on reset (por) hpreg1 uses an internal ballast to support the core current. hpreg2 is used only when external npn transistor is present on board to supply core current. the mpc5643l always powers up using hpreg1 if an external npn transistor is present. then the mpc5643l makes a transition from hpreg1 to hpreg2. th is transition is dynamic. once hpreg2 is fully operational, the controller part of hpreg1 is switched off. 3v esd(cdm) sr electrostatic discharge (charged device model) t a =25c conforming to aec-q100-011 c3a 500 v 750 (corners) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the devic e no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicabl e device specification at room temperature followed by hot temperature, unles s specified otherwise in the device specification. 3. data based on characterization results, not tested in production. table 16. esd ratings (1), (2) (continued) no. symbol parameter conditions class max value (3) unit table 17. latch-up results no. symbol parameter conditions class 1 lu sr static latch-up class t a = 125 c conforming to jesd 78 ii level a
spc56xl60/54 electrical characteristics doc id 15457 rev 8 105/160 the following bipolar transistors are supported: bcp68 from on semiconductor bcx68 from infineon the recommended external ballast transistor is the bipolar transistor bcp68 with the gain range of 85 up to 375 (for ic=500ma, vce=1v) provided by several suppliers. this includes the gain variations bcp68-10, bcp68-16 and bcp68-25.the most important parameters for the interoperability with the integrated voltage regulator are the dc current gain (hfe) and the temperature coefficient of the gain (xtb). while the specified gain range of most bcp68 vendors is the same, there are slight variations in the temperature coefficient parameter. mpc5643lvoltage regulator operation was simulated against the typical variation on temperature coefficient and against the specified gain range to have a robust design. table 18. recommended operating characteristics symbol parameter value unit h fe ( ) dc current gain (beta) 85 - 375 ? p d maximum power dissipation @ t a =25c (1) 1. derating factor 12mw/degc 1.5 w i cmaxdc maximum peak collector current 1.0 a vce sat collector-to-emit ter saturation voltage(max) 600 (2) 2. adjust resistor at bipolar transisto r collector for 3.3v to avoid vce electrical characteristics spc56xl60/54 106/160 doc id 15457 rev 8 ? main high voltage power - low voltage detection, upper threshold ???2.9v ?d main supply low voltage detector, lowe r threshold ?2.6??v ?d digital supply high voltage detector upper threshold before a destructive reset initialization phase completion 1.355 ? 1.495 v after a destructive reset initialization phase completion 1.39 ? 1.47 ?d digital supply high voltage detector lower threshold before a destructive reset initialization phase completion 1.315 ? 1.455 v after a destructive reset initialization phase completion 1.35 ? 1.38 ?d digital supply low voltage detector lower threshold before a destructive reset initialization phase completion 1.080 ? 1.140 v ?d digital supply low voltage detector upper threshold after a destructive reset initialization phase completion 1.16 ? 1.22 v ?d por rising/ falling supply threshold voltage ? 1.6 ? 2.6 v ? sr supply ramp rate ? 3 ? 0.5 10 6 v/s ?d lvd_main: time constant of rc filter at lvd input 3.3v noise rejection at the input of lvd comparator 1.1 ? ? s ?d hvd_dig: time constant of rc filter at lvd input 1.2v noise rejection at the input of lvd comparator 0.1 ? ? s ?d lvd_dig: time constant of rc filter at lvd input 1.2v noise rejection at the input of lvd comparator 0.1 ? ? s table 19. voltage regulator electr ical specifications (continued) symbol parameter conditions min typ max unit
spc56xl60/54 electrical characteristics doc id 15457 rev 8 107/160 figure 5. bcp68 board schematic example note: the combined esr of the capacitors used on 1. 2 v pins (v1v2 in the picture) shall be in the range of 1 m to 100 m . the minimum value of the esr is constrained by the resonance caused by the external components, bonding inductance, and internal decoupling. the minimum esr is required to avoid the resonance and make the regulator stable. 3.9 dc electrical characteristics ta bl e 2 0 gives the dc electrical characteristics at 3.3 v (3.0 v < v dd_hv_io x <3.6v). bcrtl c ext c int r b l b r s v1v2 ring on board v dd v1v2 pin esr c v1v2 spc56xl60/54 bcp68 table 20. dc electrical characteristics (1) symbol parameter conditions min typ max unit v il d minimum low level input voltage ? ?0.1 (2) ?? v v il p maximum level input voltage ? ? ? 0.35 v dd_hv_iox v v ih p minimum high level input voltage ? 0.65 v dd_hv_iox ?? v v ih d maximum high level input voltage ? ? ? v dd_hv_iox +0.1 (2) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_io x ?? v v ol_s p slow, low level output voltage i ol =1.5ma ? ? 0.5 v
electrical characteristics spc56xl60/54 108/160 doc id 15457 rev 8 3.10 supply current characteristics current consumption data is given in ta bl e 2 1 . these specifications are design targets and are subject to change per device characterization. v oh_s p slow, high level output voltage i oh = ? 1.5 ma v dd_hv_io x ? 0.8 ?? v v ol_m p medium, low level output voltage i ol =2ma ? ? 0.5 v v oh_m p medium, high level output voltage i oh =?2ma v dd_hv_iox ? 0.8 ?? v v ol_f p fast, high level output voltage i ol =1.5ma ? ? 0.5 v v oh_f p fast, high level output voltage i oh =? 1.5 ma v dd_hv_io x ? 0.8 ?? v v ol_sym p symmetric, high level output voltage i ol =1.5ma ? ? 0.5 v v oh_sym p symmetric, high level output voltage i oh =? 1.5 ma v dd_hv_io x ? 0.8 ?? v i inj t dc injection current per pin ? ?1 ? 1 ma i pu p equivalent pull-up current v in =v il ?130 ? ? a v in =v ih ? ? ?10 i pd p equivalent pull-down current v in =v il 10 ? ? a v in =v ih ? ? 130 i il p input leakage current (all bidirectional ports) t j = ?40 to +150 c -1 ? 1 a input leakage current (all adc input-only ports) -0.5 ? 0.5 input leakage current (shared adc input-only ports) -1 ? 1 v ilr p reset , low level input voltage ? ?0.1 (2) ?0.35v dd_hv_io x v v ihr p reset , high level input voltage ? 0.65 v dd_hv_io x ?v dd_hv_iox +0.1 (2) v v hysr d reset , schmitt trigger hysteresis ? 0.1 v dd_hv_io x ?? v v olr d reset , low level output voltage i ol =2ma ? ? 0.5 v i pd d reset , equivalent pull-down current v in =v il 10 ? ? a v in =v ih ? ? 130 1. these specifications are des ign targets and subject to ch ange per device characterization. 2. ?sr? parameter values must not exc eed the absolute maximum ratings shown in table 9 . table 20. dc electrical characteristics (1) (continued) symbol parameter conditions min typ max unit
spc56xl60/54 electrical characteristics doc id 15457 rev 8 109/160 table 21. current consumption characteristics symbol parameter conditions (1) min typ max unit i dd_lv_full +i dd_lv_pll t operating current 1.2 v supplies t j =ambient v dd_lv_cor =1.32v ?? 50 ma+ 2.18 ma*f cpu [mhz] ma 1.2 v supplies t j = 150 c v dd_lv_cor =1.32v ?? 80 ma+ 2.50 ma*f cpu [mhz] i dd_lv_typ +i dd_lv_pll (2) t operating current 1.2 v supplies t j =ambient v dd_lv_cor =1.32v ?? 26 ma+ 2.10 ma*f cpu [mhz] ma 1.2 v supplies t j = 150 c v dd_lv_cor =1.32v ?? 41 ma+ 2.30 ma*f cpu [mhz] i dd_lv_typ +i dd_lv_pll (2) p operating current 1.2 v supplies t j =ambient v dd_lv_cor =1.32v ?? 279ma ma 1.2 v supplies t j = 150 c v dd_lv_cor =1.32v ?? 318ma i dd_lv_bist +i dd_lv_pll t operating current 1.2 v supplies during lbist (full lbist configuration) t j =ambient v dd_lv_cor =1.32v ?? 250 ma 1.2 v supplies during lbist (full lbist configuration) t j = 150 c v dd_lv_cor =1.32v ?? 290 i dd_lv_typ + i dd_lv_pll t operating current 1.2v supplies tj=105c v dd_lv_cor = 1.2v ?? 275 ma i dd_lv_typ + i dd_lv_pll t operating current 1.2v supplies tj=125c v dd_lv_cor = 1.2v ?? 299 ma i dd_lv_typ + i dd_lv_pll t operating current 1.2v supplies tj=105c v dd_lv_cor = 1.2v dpm mode ?? 189 ma i dd_lv_typ + i dd_lv_pll t operating current 1.2v supplies tj=125c v dd_lv_cor = 1.2v dpm mode ?? 214 ma
electrical characteristics spc56xl60/54 110/160 doc id 15457 rev 8 i dd_lv_typ + i dd_lv_pll t operating current 1.2v supplies tj=150c v dd_lv_cor = 1.2v dpm mode ?? 253 ma i dd_lv_stop t operating current in v dd stop mode t j =ambient v dd_lv_cor =1.32v ?? 50 ma t t j =55 c v dd_lv_cor =1.32v ?? 57 p t j = 150 c v dd_lv_cor =1.32v ?? 72 i dd_lv_halt t operating current in v dd halt mode t j =ambient v dd_lv_cor =1.32v ?? 58 ma t t j =55 c v dd_lv_cor =1.32v ?? 64 p t j = 150 c v dd_lv_cor =1.32v ?? 80 i dd_hv_adc (3), (4) t operating current t j = 150 c 120 mhz adc operating at 60 mhz v dd_hv_adc =3.6v ?? 10 ma i dd_hv_aref (4) t operating current t j = 150 c 120 mhz adc operating at 60 mhz v dd_hv_ref =3.6v ?? 3 ma t j = 150 c 120 mhz adc operating at 60 mhz v dd_hv_ref =5.5v ?? 5 i dd_hv_osc t operating current t j = 150 c 3.3 v supplies 120 mhz ?? 900 a i dd_hv_flash (5) t operating current t j = 150 c 3.3 v supplies 120 mhz ?? 4 ma 1. devices configured for dpm mode, single core only with core 0 executing typical code at 120 mhz from sram and core 1 in reset. if core execution mode not specif ied, the device is configured for lsm m ode with both cores executing typical code at 120 mhz from sram. 2. enabled modules in 'typical mode': flex pwm0, etimer0/1/2, ctu, swg, dma, flexcan0/1, linflex, adc1, dspi0/1, pit, crc, pll0/1, i/o supply current excluded 3. internal structures hold the input vo ltage less than vdda + 1.0 v on all pads powered by vdda supplies, if the maximum injection current specification is met (3 ma for all pins) and vdda is within the operating voltage specifications. table 21. current consumption characteristics (continued) symbol parameter conditions (1) min typ max unit
spc56xl60/54 electrical characteristics doc id 15457 rev 8 111/160 3.11 temperature sensor electrical characteristics 3.12 main oscillator elec trical characteristics the device provides an os cillator/resonator driver. figure 6 describes a simple model of the internal oscillator driver and provides an example of a conn ection for an oscillator or a resonator. figure 6. crystal oscillator and resonator connection scheme note: xtal/extal must not be directly used to drive external circuits. 4. this value is the total current for both adcs. 5. vflash is only available in the calibration package. table 22. temperature sensor electrical characteristics symbol parameter conditions min max unit ? p accuracy t j = ?40 c to 150 c ?10 10 c t s d minimum sampling period ? 4 ? s c l c l crystal xtal extal r p resonator xtal extal device device device xtal extal i r v dd
electrical characteristics spc56xl60/54 112/160 doc id 15457 rev 8 figure 7. main oscillator electrical characteristics v xoschsop t xoschssu v xtal v xoschs valid internal clock 90% 10% 1/f xoschs mtrans 1 0 table 23. main oscillator el ectrical char acteristics symbol parameter conditions (1) value unit min typ max f xoschs s r oscillator frequency ? 4.0 ? 40.0 mhz g mxoschs p oscillator transconductance v dd = 3.3 v 10% 4.5 ? 13.25 ma/v v xoschs d oscillation amplitude f osc = 4, 8, 10, 12, 16 mhz 1.3 ? ? v f osc =40mhz 1.1 ? ? v xoschsop d oscillation operating point ? ? 0.82 ? v i xoschs d oscillator consumption ? ? ? 3.5 ma t xoschssu t oscillator start-up time f osc = 4, 8, 10, 12 mhz (2) ?? 6 ms f osc =16, 40mhz (2) ?? 2 v ih s r input high level cmos schmitt trigger oscillator bypass mode 0.65 v d d ?v dd +0.4 v v il s r input low level cmos schmitt trigger oscillator bypass mode ?0.4 ? 0.35 v dd v 1. v dd = 3.3 v 10%, t j = ?40 to +150 c, unless otherwise specified. 2. the recommended configuration for maxi mizing the oscillator margin are: xosc_margin = 0 for 4 mhz quartz xosc_margin = 1 for 8/16/40 mhz quartz
spc56xl60/54 electrical characteristics doc id 15457 rev 8 113/160 3.13 fmpll electrical characteristics table 24. fmpll electrical characteristics symbol parameter conditions min typ max unit f ref_crystal f ref_ext d fmpll reference frequency range (1) crystal reference 4 ? 40 mhz f pll_in d phase detector input frequency range (after pre- divider) ?4?16mhz f fmpllout d clock frequency range in normal mode ? 4 ? 120 (2) mhz f free p free running frequency measured using clock division (typically 16) 20 ? 150 mhz f sys d on-chip fmpll frequency (2) ?16?120mhz t cyc d system clock period ? ? ? 1 / f sys ns f lorl f lorh d loss of reference frequency window (3) lower limit 1.6 ? 3.7 mhz upper limit 24 ? 56 f scm d self-clocked mode frequency (4),(5) ?20?150mhz t lock p lock time stable oscillator (f pllin = 4 mhz), stable v dd ??200 s t lpll d fmpll lock time (6), (7) ???200 s t dc d duty cycle of reference ?40?60% c jitter t clkout period jitter (8),(9),(10),(11) long-term jitter (avg. over 2 ms interval), f fmpllout maximum ?6 ? 6 ns t pkjit t single period jitter (peak to peak) phi @ 120 mhz, input clock @ 4 mhz ??175 ps phi @ 100 mhz, input clock @ 4 mhz ??185 ps phi @ 80 mhz, input clock @ 4 mhz ??200 ps t ltjit t long term jitter phi @ 16 mhz, input clock @ 4 mhz ??6 ns f lck d frequency lock range ? ?6 ? 6 % f fmpllout f ul d frequency un-lock range ? ?18 ? 18 % f fmpllout f cs f ds d modulation depth center spread 0.25 ? 2.0 % f fmpllout down spread ?0.5 ? -8.0 f mod d modulation frequency (12) ? ? ? 100 khz 1. considering operation wi th fmpll not bypassed. 2. with fm; the value does not include a possible +2% modulation
electrical characteristics spc56xl60/54 114/160 doc id 15457 rev 8 3.14 16 mhz rc oscillator el ectrical characteristics 3.15 adc electrical characteristics the device provides a 12-bit successive approximation register (sar) analog-to-digital converter. 3. ?loss of reference frequency? window is the reference frequency range outside of which the fmpll is in self clocked mode. 4. self clocked mode frequency is the frequency that the fmp ll operates at when the reference frequency falls outside the f lor window. 5. f vco is the frequency at the output of the vco; its range is 256?512 mhz. f scm is the self-clocked mode frequency (fre e running frequency); its range is 20?150 mhz. f sys =f vco odf 6. this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this fmpll, load capacitors shoul d not exceed these limits. 7. this specification applies to the period required for the fmpll to relock after c hanging the mfd frequency control bits in the synthesizer control register (syncr). 8. this value is determined by the crystal manufacturer and board design. 9. jitter is the average deviation from t he programmed frequency measured over t he specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fmpll circuitry via v ddpll and v sspll and variation in crystal osci llator frequency increase the c jitter percentage for a given interval. 10. proper pc board layout procedures must be followed to achieve specifications. 11. values are with frequency modulati on disabled. if frequency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 12. modulation depth is attenuated from depth setting wh en operating at modulation frequencies above 50 khz. table 25. rc oscillator electrical characteristics symbol parameter conditions min typical max unit f rc p rc oscillator frequency ? 15.04 16 16.96 mhz
spc56xl60/54 electrical characteristics doc id 15457 rev 8 115/160 figure 8. adc characteristi cs and error definitions 3.15.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capa citor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high- impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited acco rding to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 7.5 pf, a resistance of 133 k is obtained (r eq =1 / (f c c s ), where fc represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s +r f , the external circuit must be designed to respect the equation 4 : (2 ) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 1 lsb ideal =(vrefh-vrefl)/ 4096 = 3.3v/ 4096 = 0.806 mv total unadjusted error tue = +/- 6 lsb = +/- 4.84mv
electrical characteristics spc56xl60/54 116/160 doc id 15457 rev 8 equation 4 equation 4 generates a constraint for external network design, in particular on resistive path. internal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 9. input equivalent circuit a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 9 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). v a r s r f + r eq --------------------- ? 1 2 -- -lsb < r f c f r s r l r sw1 c p2 v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a c s
spc56xl60/54 electrical characteristics doc id 15457 rev 8 117/160 figure 10. transient behavior during sampling phase in particular two different transient periods can be distinguished: a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time cons tant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 ) 1 r sw r ad + () = c p c s ? c p c s + --------------------- - ? 1 r sw r ad + () < c s t s ? ? v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? =
electrical characteristics spc56xl60/54 118/160 doc id 15457 rev 8 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 11. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at 2 r l < c s c p1 c p2 ++ () ? 10 2 ? 10 r l c s c p1 c p2 ++ () ? ? =t s < v a2 c s c p1 c p2 c f +++ () ? v a c f ? v a1 +c p1 c p2 +c s + () ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c 2 r f c f (conversion rate vs. filter pole) noise
spc56xl60/54 electrical characteristics doc id 15457 rev 8 119/160 least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new c onstraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 8192 c s ? > table 26. adc conversion characteristics symbol parameter conditions (1) min typ max unit f ck s r adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_ck (2) frequency) ?3?60mhz f s s r sampling frequency ? ? ? 983.6 (3) khz t sample d sample time (4) 60 mhz 383 ? ? ns t conv dconversion time (5) 60 mhz 600 ? ? ns c s (6) d adc input sampling capacitance ? ? ? 7.32 pf c p1 (6) d adc input pin capacitance 1 ? ? ? 5 ((7)) pf c p2 (6) d adc input pin capacitance 2 ? ? ? 0.8 pf r sw1 (6) d internal resistance of analog source v ref range = 4.5 to 5.5 v ? ? 0.3 k v ref range = 3.0 to 3.6 v ? ? 875 w r ad (6) d internal resistance of analog source ? ? ? 825 w inl p integral non linearity ? ?3 ? 3 lsb dnl p differential non linearity (8) ??1?2lsb ofs t offset error ? ?6 ? 6 lsb gne t gain error ? ?6 ? 6 lsb
electrical characteristics spc56xl60/54 120/160 doc id 15457 rev 8 3.16 flash memory elect rical characteristics is1winj (single adc channel) max leakage 150c ? ? 250 na max positive/negative injection ?3 ? 3 ma is1wwinj (double adc channel) max leakage 150c ? ? 300 na max positive/negative injection |vref_ad0 - vref_ad1| < 150mv ?3.6 ? 3.6 ma snr t signal-to-noise ratio vref = 3.3v 67 ? ? db snr t signal-to-noise ratio vref = 5.0v 69 ? ? db thd t total harmonic distortion ? -65 ? ? db sinad t signal-to-noise and distortion ? 65 ? ? db enob t effective number of bits ? 10.5 ? ? bits tue is1winj t total unadjusted error for is1winj (single adc channels) without current injection ?6 ? 6 lsb with current injection ?8 ? 8 lsb tue is1wwinj p total unadjusted error for is1wwinj (double adc channels) without current injection ?8 ? 8 lsb t with current injection ?10 ? 10 lsb 1. v dd = 3.3 v, t j = ?40 to +150 c, unless otherwise s pecified and analog input voltage from v agnd to v aref . 2. ad_ck clock is always half of the adc module input cl ock defined via the auxiliary clock divider for the adc. 3. this is the maximum frequency that the analog portion of t he adc can attain. a sustained conversion at this frequency is not possible. 4. during the sample time the input capacitance cs can be charged/discharged by the exte rnal source. the internal resistance of the analog source must allow the capa citance to reach its final voltage level within t sample . after the end of the sample time t sample , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t sample depend on programming. 5. this parameter does not include the sample time t sample , but only the time for determining the digital result and the time to load the result register wi th the conversion result. 6. see figure 9 . 7. for the 144-pin package 8. no missing codes table 26. adc conversion characteristics (continued) symbol parameter conditions (1) min typ max unit table 27. flash memory program and erase electrical specifications no. symbol parameter typ (1) factory avg initial max (2) lifetime max (3) unit 1t dwprogram * (4) double word (64 bits) program time (4) 38 ? ? 500 s 2t pprogram * (5) page(128 bits) program time (5) 45 53 160 500 s 3t 16kpperase * (5) 16 kb block pre-program and erase time 270 1000 500 5000 ms 4t 48kpperase * (5) 48 kb block pre-program and erase time 625 1500 750 5000 ms
spc56xl60/54 electrical characteristics doc id 15457 rev 8 121/160 5t 64kpperase * (5) 64 kb block pre-program and erase time 800 1800 900 5000 ms 6t 128kpperase * (5) 128 kb block pre-program and erase time 1500 2600 1300 7500 ms 7t 256kpperase * (5) 256 kb block pre-program and erase time 3000 5200 2600 15000 ms 1. typical program and eras e times represent the median performanc e and assume nominal supply values and operation at 25c. these values are characterized, but not tested.i 2. initial max program and erase times provide guidance fo r time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supp ly values and operation at 25c. thes e values are verified at production test. 3. lifetime max program and erase time s apply across the voltage, temper ature, and cycling range of product life. these values are char acterized, but not tested. 4. program times are actual hardware progra mming times and do not include software overhead. 5. program times are actual hardware progra mming times and do not include software overhead. table 27. flash memory program and erase electrical specifications no. symbol parameter typ (1) factory avg initial max (2) lifetime max (3) unit table 28. flash memory timing symbol parameter value unit min typ max t res d time from clearing the mcr-esus or psus bit with ehv = 1 until done goes low ??100ns t done d time from 0 to 1 transition on the mcr-ehv bit initiating a program/erase until the m cr-done bit is cleared ?? 5ns t psrt d time between program suspend resume and the next program suspend request. (1) 100 ? ? s t esrt d time between erase suspend resume and the next erase suspend request. (2) 10 ms 1. repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0), or the operation not able to finish (mcr[done] = 1 during program operation). the minimu m time between suspends to ensure this does not occur is t psrt . 2. if erase suspend rate is less than t esrt , an increase of slope voltage ramp occurs during erase pulse. this improves eras e time but reduces cycling figure due to overstress
electrical characteristics spc56xl60/54 122/160 doc id 15457 rev 8 3.17 swg electrical characteristics table 29. flash memory module life no. symbol parameter value unit minimum typical maximum 1p/ec number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range (1) 100000 ? ? cycles 2p/ec number of program/erase cycles per block for 128 kb and 256 kb blocks over the operating temperature range (1) 1000 100000 (2) ? cycles 3 retention c minimum data retention at 85 c average ambient temperature (3) blocks with 0?1,000 p/e cycles blocks with 1,001?10,000 p/e cycles blocks with 10,001?100,000 p/e cycles 20 10 5 ? ? ? ? ? ? years 1. operating temperature range is t j from ?40 c to 150 c. typical endurance is evaluated at 25 c. 2. typical p/e cycles is 100,000 cycles for 128 kb and 256 kb blocks. 3. ambient temperature averaged over dur ation of application, not to exceed product operating temperature range. table 30. mpc5643l swg specifications symbol parameter value minimum typical maximum t input clock 12 mhz 16 mhz 20 mhz t frequency range 1khz ? 50 khz t peak to peak (1) 0.4 v ? 2.0v t peak to peak variation (2) -6% ? 6% t common mode (3) ? 1.3 v ? t common mode variation -6% ? 6% t sinad (4) 45 db ? ? t load c 25 pf ? 100 pf t load i 0 a ? 100 a t esd pad resistance (5) 230 ?360 1. peak to peak value is measured with no r or i load. 2. peak to peak excludes noise , sinad must be considered. 3. common mode value is measured with no r or i load. 4. sinad is measured at max peak to peak voltage. 5. internal device routing resistance. esd pad resistance is in series and must be considered for max peak to peak voltages, depending on application i load and/or r load.
spc56xl60/54 electrical characteristics doc id 15457 rev 8 123/160 3.18 ac specifications 3.18.1 pad ac specifications table 31. pad ac specificat ions (3.3 v , ipp_hve = 0 ) (1) no. pad tswitchon (1) (ns) rise/fall (2) (ns) frequency (mhz) current slew (3) (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1slowt 3 ? 40 ? ? 40 ? ? 4 0.01 ? 2 25 3 ? 40 ? ? 50 ? ? 2 0.01 ? 2 50 3 ? 40 ? ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 ? ? 100 ? ? 2 0.01 ? 2 200 2 medium t 1 ? 15 ? ? 12 ? ? 40 2.5 ? 7 25 1 ? 15 ? ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 ? ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 ? ? 70 ? ? 7 2.5 ? 7 200 3fastt 1?6??4??723?40 25 1?6??7??557?40 50 1 ? 6 ? ? 12 ? ? 40 7 ? 40 100 1 ? 6 ? ? 18 ? ? 25 7 ? 40 200 4 symmetric t 1 ? 8 ? ? 5 ? ? 50 3 ? 25 25 1. propagation delay from v dd_hv_io x /2 of internal signal to pchannel /nchannel switch-on condition. 2. slope at rising/falling edge. 3. data based on characterization results, not tested in production.
electrical characteristics spc56xl60/54 124/160 doc id 15457 rev 8 figure 12. pad output delay 3.19 reset sequence this section shows the duration for different reset sequences. it describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences. 3.19.1 reset sequence duration ta bl e 3 2 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in section 3.19.2, reset sequence description . v dde /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output table 32. reset sequences no. symbol parameter conditions t reset unit min typ max (1) 1t drb cc destructive reset sequence, bist enabled 40 47 51 ms 2t dr cc destructive reset sequence, bist disabled ? 500 4200 5000 s 3t erlb cc external reset sequence long, bist enabled 41 45 49 ms 4t frl cc functional reset sequence long ? 35 150 400 s 5t frs cc functional reset sequence short ? 1 4 10 s 1. the maximum value is applicable only if the reset sequence duration is not pr olonged by an extended assertion of reset by an external reset generator.
spc56xl60/54 electrical characteristics doc id 15457 rev 8 125/160 3.19.2 reset sequence description the figures in this section show the internal states of the chip during the five different reset sequences. the doted lines in the figures indicate the starting point and the end point for which the duration is specified in ta bl e 3 2 . the start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in section 3.19.3, reset sequence trigger mapping . with the beginning of drun mode the first instruction is fetched and executed. at this point application execution starts and the internal reset sequence is finished. the figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the signal pin reset . note: reset is a bidirectional pin. the voltage level on this pin can either be driven low by an external reset generator or by the chip internal reset circuitry. a high level on this pin can only be generated by an external pull up resistor which is strong enough to overdrive the weak internal pull down resi stor. the rising edge on reset in the following figures indicates the time when the device stops driving it low. the reset sequence durations given in table ta bl e 3 2 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping reset asserted low beyond the last phase3. figure 13. destructive reset sequence, bist enabled figure 14. destructive reset sequence, bist disabled phase3 bist phase1,2 phase0 phase1,2 phase3 establish irc and pwr flash init device config self test setup drun lbist mbist flash init device config application execution t drb, min < t reset < t drb, max reset sequence start condition reset sequence trigger reset_b reset phase3 phase1,2 phase0 establish irc and pwr flash init device config drun application execution t dr, min < t reset < t dr, max reset sequence trigger reset sequence start condition reset_b reset
electrical characteristics spc56xl60/54 126/160 doc id 15457 rev 8 figure 15. external reset sequence long, bist enabled figure 16. functional reset sequence long figure 17. functional reset sequence short phase3 bist phase1,2 phase1,2 phase3 flash init device config self test setup drun lbist mbist flash init device config application execution t erlb, min < t reset < t erlb, max reset sequence trigger reset sequence start condition reset_b reset phase3 phase1,2 flash init device config drun application execution t frl, min < t reset < t frl, max reset sequence trigger reset sequence start condition reset_b reset phase3 drun application execution t frs, min < t reset < t frs, max reset sequence trigger reset sequence start condition reset_b reset
spc56xl60/54 electrical characteristics doc id 15457 rev 8 127/160 the reset sequences shown in figure 16 and figure 17 are triggered by functional reset events. reset is driven low during these two reset sequences only if the corresponding functional reset source (which triggered th e reset sequence) was enabled to drive reset low for the duration of the internal reset sequence (c) . 3.19.3 reset sequence trigger mapping the following table shows the possible trigger events for the different reset sequences. it specifies the reset sequence start conditions as well as the reset sequence end indications that are the basis for the timing data provided in ta b l e 3 2 . c. see rgm_fbre register for more details. table 33. reset sequence trigger ? reset sequence reset sequence trigger reset sequence start condition reset sequence end indication reset sequence destructiv e reset sequence, bist enabled (1) destructiv e reset sequence, bist disabled (1) external reset sequenc e long, bist enabled functiona l reset sequenc e long functiona l reset sequenc e short all internal destructive reset sources (lvds or internal hvd during power-up and during operation) section , destructive reset release of reset (2) triggers cannot trigger cannot trigger cannot trigger assertion of reset (3) section , external reset via reset cannot trigger triggers (4) triggers (5) triggers (6) all internal functional reset sources configured for long reset sequence starts with internal reset trigger release of reset (7) cannot trigger cannot trigger triggers cannot trigger all internal functional reset sources configured for short reset cannot trigger cannot trigger cannot trigger triggers 1. whether bist is executed or not depend s on the chip configuration data stored in the shadow sector of the nvm. 2. end of the internal reset sequence (as specified in table 32 ) can only be observed by release of reset if it is not held low externally beyond the end of the internal sequence which would prolong the internal reset phase3 till reset is released externally.
electrical characteristics spc56xl60/54 128/160 doc id 15457 rev 8 3.19.4 reset sequence ? start condition the impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration. destructive reset figure 18 shows the voltage threshold that determines the start of the destructive reset sequence, bist enabled and the start for the destructive reset sequence, bist disabled . figure 18. reset sequence start for destructive resets 3. the assertion of reset can only trigger a reset sequence if the device was running (reset released) before. reset does not gate a destructive reset sequence, bist enabled or a destructive reset sequence, bist disabled . however, it can prolong these sequences if reset is held low externally beyond the end of the internal sequence (beyond phase3). 4. if reset is configured for long reset (default) and if bist is enabl ed via chip configuration data stored in the shadow sector of the nvm. 5. if reset is configured for long reset (default) and if bist is disabled via chip c onfiguration data stored in the shadow sector of the nvm. 6. if reset is configured for short reset 7. internal reset sequence can only be observed by state of reset if bidirectional reset functionality is enabled for the functional reset source which triggered the reset sequence. table 34. voltage thresholds variable name value v min refer to ta b l e 1 9 v max refer to ta b l e 1 9 supply rail vdd_hv_pmu t reset, max starts here t reset, min starts here supply rail v max t v v min
spc56xl60/54 electrical characteristics doc id 15457 rev 8 129/160 external reset via reset figure 19 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of reset as specified in ta bl e 3 3 . figure 19. reset sequ ence start via reset assertion 3.19.5 external watchdog window if the application design requires the use of an external watchdog the data provided in section 3.19, reset sequence can be used to determine the correct positioning of the trigger window for the external watchdog. figure 20 shows the relationships between the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window. figure 20. reset sequence - extern al watchdog trigger window position t reset, max starts here t reset, min starts here reset_b 0.65 * vdd_hv_io t v 0.35 * vdd_hv_io reset external watchdog window closed earliest application start latest application start internal reset sequence start condition (signal or voltage rail) external watchdog window open t reset, min t reset, max t wdstart, min t wdstart, max external watchdog window closed external watchdog window open basic application init basic application init application time required to prepare watchdog trigger watchdog needs to be triggered within this window watchdog trigger application running application running
electrical characteristics spc56xl60/54 130/160 doc id 15457 rev 8 3.20 ac timing characteristics ac test timing conditions: unless otherwise noted, all test conditions are as follows: ? tj = ?40 to 150 c ? supply voltages as specified in ta bl e 1 0 ? input conditions: all inputs: tr, tf = 1 ns ? output loading: all outputs: 50 pf 3.20.1 reset pin characteristics the spc56xl60/54 im plements a dedicate d bidirectional reset pin. figure 21. start-up reset requirements figure 22. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
spc56xl60/54 electrical characteristics doc id 15457 rev 8 131/160 3.20.2 wkup/nmi timing 3.20.3 ieee 1149.1 jtag interface timing table 35. reset electrical characteristics no. symbol parameter conditions (1) min typ max unit 1t tr d output transition time output pin (2) c l =25pf ? ? 12 ns c l =50pf ? ? 25 c l = 100pf ? ? 40 2w frst p nreset input filtered pulse ? ? ? 40 ns 3w nfrst p nreset input not filtered pulse ? 500 ? ? ns 1. v dd = 3.3 v 10%, t j = ?40 to +150 c, unless otherwise specified 2. c l includes device and package capacitance (c pkg <5pf). table 36. wkup/nmi glitch filter no. symbol parameter min typ max unit 1w fnmi d nmi pulse width that is rejected ? ? 45 ns 2w nfnmi d nmi pulse width that is passed 205 ? ? ns table 37. jtag pin ac electrical characteristics no. symbol parameter conditions min max unit 1t jcyc d tck cycle time ? 62.5 ? ns 2t jdc d tck clock pulse width (measured at v dde /2) ? 40 60 % 3t tckrise d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis d tms, tdi data setup time ? 5 ? ns 5t tmsh, t tdih d tms, tdi data hold time ? 25 ? ns 6t tdov d tck low to tdo data valid ? ? 20 ns 7t tdoi d tck low to tdo data invalid ? 0 ? ns 8t tdohz d tck low to tdo high impedance ? ? 20 ns 11 t bsdv d tck falling edge to output valid ? ? 50 ns 12 t bsdvz d tck falling edge to output valid out of high impedance ? ? 50 ns 13 t bsdhz d tck falling edge to output high impedance ? ? 50 ns 14 t bsdst d boundary scan input valid to tck rising edge ? 50 ? ns 15 t bsdht d tck rising edge to boundary scan input invalid ? 50 ? ns
electrical characteristics spc56xl60/54 132/160 doc id 15457 rev 8 figure 23. jtag test clock input timing figure 24. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
spc56xl60/54 electrical characteristics doc id 15457 rev 8 133/160 figure 25. jtag boundary scan timing 3.20.4 nexus timing tck output signals input signals output signals 11 12 13 14 15 table 38. nexus debug port timing (1) no. symbol parameter conditions min max unit 1t mcyc d mcko cycle time ? 15.6 ? ns 2t mdc d mcko duty cycle ? 40 60 % 3t mdov d mcko low to mdo, mseo , evto data valid (2) ? ?0.1 0.25 t mcy c 4t evtipw d evti pulse width ? 4.0 ? t tcy c 5t evtopw d evto pulse width ? 1 t mcy c 6t tcyc d tck cycle time (3) ? 62.5 ? ns 7t tdc d tck duty cycle ? 40 60 % 8 t ntdis, t ntmss d tdi, tms data setup time ? 8 ? ns
electrical characteristics spc56xl60/54 134/160 doc id 15457 rev 8 figure 26. nexus output timing figure 27. nexus evti input pulse width 9 t ntdih, t ntmsh d tdi, tms data hold time 5 ? ns 10 t jov d tck low to tdo/rdy data valid 0 25 ns 1. jtag specifications in this table appl y when used for debug functionality. all nexu s timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2. for all nexus modes except ddr mode, mdo, mseo , and evto data is held valid unt il next mcko low cycle. 3. the system clock frequency needs to be f our times faster than the tck frequency. table 38. nexus debug port timing (1) (continued) no. symbol parameter conditions min max unit 1 2 mcko mdo mseo evto output data valid 3 5 4 evti
spc56xl60/54 electrical characteristics doc id 15457 rev 8 135/160 figure 28. nexus double data rate (ddr) mode output timing mcko mdo, mseo mdo/mseo data are valid during mcko rising and falling edge
electrical characteristics spc56xl60/54 136/160 doc id 15457 rev 8 figure 29. nexus tdi, tms, tdo timing 3.20.5 external interr upt timing (irq pin) tdo/rdy 8 9 tms, tdi 10 tck 6 7 table 39. external interrupt timing no. symbol parameter conditions min max unit 1t ipwl d irq pulse width low ? 3 ? t cyc 2t ipwh d irq pulse width high ? 3 ? t cyc 3t icyc d irq edge to edge time (1) ?6?t cyc 1. applies when irq pins are configured for rising edge or falling edge events, but not both.
spc56xl60/54 electrical characteristics doc id 15457 rev 8 137/160 figure 30. external interrupt timing 3.20.6 dspi timing irq 1 2 3 table 40. dspi timing no. symbol parameter conditions min max unit 1t sck d dspi cycle time master (mtfe = 0) 62 ? ns d slave (mtfe = 0) 62 ? d slave receive only mode (1) 16 ? 2t csc d pcs to sck delay ? 16 ? ns 3t asc d after sck delay ? 16 ? ns 4t sdc d sck duty cycle ? t sck /2 - 10 t sck /2 + 10 ns 5t a d slave access time ss active to sout valid ? 40 ns 6t dis d slave sout disable time ss inactive to sout high-z or invalid ? 10 ns 7t pcsc d pcsx to pcss time ? 13 ? ns 8t pasc dpcss to pcsx time ? 13 ? ns 9t sui d data setup time for inputs master (mtfe = 0) 20 ? ns slave 2? master (mtfe = 1, cpha = 0) 5? master (mtfe = 1, cpha = 1) 20 ? 10 t hi d data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? 11 t suo d data valid (after sck edge) master (mtfe = 0) ? 4 ns slave ? 23 master (mtfe = 1, cpha = 0) ? 12 master (mtfe = 1, cpha = 1) ? 4
electrical characteristics spc56xl60/54 138/160 doc id 15457 rev 8 figure 31. dspi classic spi timing ? master, cpha = 0 12 t ho d data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ?2 ? 1. slave receive only mode can operate at a maximum frequency of 60 mhz. in this mode, the dspi can receive data on sin, but no valid data is transmitted on sout. table 40. dspi timing (continued) no. symbol parameter conditions min max unit data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 the numbers shown are referenced in table 40 .
spc56xl60/54 electrical characteristics doc id 15457 rev 8 139/160 figure 32. dspi classic spi timing ? master, cpha = 1 figure 33. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) the numbers shown are referenced in table 40 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) the numbers shown are referenced in table 40 .
electrical characteristics spc56xl60/54 140/160 doc id 15457 rev 8 figure 34. dspi classic spi timing ? slave, cpha = 1 figure 35. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) the numbers shown are referenced in table 40 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) the numbers shown are referenced in table 40 .
spc56xl60/54 electrical characteristics doc id 15457 rev 8 141/160 figure 36. dspi modified transfer format timing ? master, cpha = 1 figure 37. dspi modified transf er format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) the numbers shown are referenced in table 40 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 the numbers shown are referenced in table 40 .
electrical characteristics spc56xl60/54 142/160 doc id 15457 rev 8 figure 38. dspi modified transfer format timing ? slave, cpha = 1 figure 39. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) the numbers shown are referenced in table 40 . pcsx 7 8 pcss the numbers shown are referenced in table 40 .
spc56xl60/54 package characteristics doc id 15457 rev 8 143/160 4 package characteristics 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.2 package mechanical data figure 40. lqfp100 package mechanical drawing
package characteristics spc56xl60/54 144/160 doc id 15457 rev 8 table 41. lqfp100 mechanical data symbol mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 tolerance mm inches ccc 0.080 0.0031
spc56xl60/54 package characteristics doc id 15457 rev 8 145/160 figure 41. lqfp144 package mechanical drawing table 42. lqfp144 mechanical data symbol mm inches (1) typ min max typ min max a 1.6 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.4 1.35 1.45 0.0551 0.0531 0.0571 b 0.22 0.17 0.27 0.0087 0.0067 0.0106 c 0.09 0.2 0.0035 0.0079 d 22 21.8 22.2 0.8661 0.8583 0.8740 d1 20 19.8 20.2 0.7874 0.7795 0.7953 d3 17.5 0.6890 e 22 21.8 22.2 0.8661 0.8583 0.8740
package characteristics spc56xl60/54 146/160 doc id 15457 rev 8 e1 20 19.8 20.2 0.7874 0.7795 0.7953 e3 17.5 0.6890 e 0.5 0.0197 l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 0.0394 k 3.5 0.0 7.0 3.5 0.0 7.0 tolerance mm inches ccc 0.08 0.0031 1. values in inches are converted fr om mm and rounded to four decimal digits. table 42. lqfp144 mechanical data (continued) symbol mm inches (1) typ min max typ min max
spc56xl60/54 package characteristics doc id 15457 rev 8 147/160 figure 42. lfbga257 package mechanical drawing table 43. lfbga257 mechanical data
package characteristics spc56xl60/54 148/160 doc id 15457 rev 8 title: lfbga 14x14x1.7 257 f17x17 pitch 0.8 ball 0.4 package code: jedec/eiaj reference number: jedec standard no.95 section 4.5 (fine pitch, square ball grid array package design guide) dimensions databook (mm) drawing (mm) ref. min. typ. max. min. typ. max. notes a 1.70 1.45 (1) a1 0.21 0.25 0.30 0.35 a2 1.085 1.03 1.085 1.14 a3 0.30 0.26 0.30 0.34 a4 0.80 0.77 0.785 0.80 b 0.35 0.40 0.45 0.35 0.40 0.45 (2) d 13.85 14.00 14.15 13.85 14.00 14.15 d1 12.80 12.80 e 13.85 14.00 14.15 13.85 14.00 14.15 e1 12.80 12.80 e 0.80 0.80 f 0.6 0.6 ddd 0.12 0.12 eee 0.15 0.15 (3) fff 0.08 0.08 (4) notes: (1) - lfbga stands for l ow profile f ine pitch b all g rid a rray. - low profile: the total profile height (dim a) is measured from the seating plane to the top of the component - the maximum total package height is calculated by the following methodology: a2 typ+a1 typ + (a12+a32+a42 tolerance values) - low profile: 1.20mm < a ? 1.70mm / fine pitch: e < 1.00mm pitch. (2) ? the typical ball diameter before mounting is 0.40mm. (3) - the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindrical tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. (4) - the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respective zone eee above the axis of each ball must lie simultaneously in both tolerance zones. (5) - the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. - a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional.
spc56xl60/54 ordering information doc id 15457 rev 8 149/160 5 ordering information figure 43. commercial product code structure (d) d. not all configurations are ava ilable on the market. please contac t your st sales rappresentative to get the list of orderable commercial part number. memory conditioning core family y=tray r = tape and reel q = quality management safety level s = asild/sil3 safety level o = no flexray f=flexray c=80mhz b = 120 mhz b = ?40 c to 105 c c = ?40 c to 125 c l3 = lqfp100 l5 = lqfp144 60 = 1 mb flash memory 54 = 768 k flash memory l = spc56xl family e = e200z4d dual core 4=single core spc56 = power architecture in 90 nm temperature package device options spc56 60 y el c l5 b example code: product identifier fq
revision history spc56xl60/54 150/160 doc id 15457 rev 8 6 revision history table 44. document revision history date revision changes 02-mar-2009 1 initial release. 05-may-2009 2 updated, advance information. ? revised sinad/snr specifications. ? updated pinout and pin multiplexing information. 29-oct-2009 3 updated, advance information, public release. ? throughout this document, added information for lfbga257 package. ? updated feature summary. ? updated ta b l e 1 , spc56xl60/54 device summary. ? updated section 1.3, feature details. ? updated pin-out and pin multiplexing tables. ? in section 3, electrical characteristics, added symbols for signal characterization methods. ?in ta b l e 9 , updated maximum ratings. ?in ta b l e 1 2 and ta b l e 1 3 , removed moving-air thermal characteristics. ? updated section 3.8, voltage regula tor electrical characteristics. ? updated section 3.14, adc electrical characteristics. ? updated section 3.15, flash memory electrical characteristics. ? updated section 3. 17.1, reset pin characteristics. ? removed external interrupt timing (irq pin) timing specifications. ? updated section 3.17.6, dspi timing. updated section 5, ordering information. 14-jun-2010 4 editorial changes and improvements. revised the 257-pin package pin pitch (was 1.4 mm, is 0.8 mm). added information about the 100-pin lqfp. in the overview section: ? renamed the peripheral bridge to ?pbridge?. ? revised the information for flexray. ? revised the ?clock, reset, power, m ode and test control module? section. ? revised the ?platform memory access time summary? table and replaced tbds by meaningful values. extensive revisions to signal descriptions and pin muxing information. in the ?recommended operating conditions (3.3 v)? table, changed the specification for v dd_hv_adr0 and v dd_hv_adr1 (was ?...3.3 v?, is ?...3.6 v?). revised the ?emi testing specifications? table. in the ?hpreg1, hpreg2, main lvds, digital hvd, and digital lvd electrical specifications? table, added a specificat ion for the digital low voltage detector upper threshold. revised the ?fmpll electric al characteristics? table.
spc56xl60/54 revision history doc id 15457 rev 8 151/160 14-jun-2010 4 (continued) in the ?main oscillator electrical characteristics? table, changed the maximum specification for g mxoschs (was 11 ma/v, is 11.8 ma/v). revised the ?adc electrical characteri stics? section.in the ?adc conversion characteristics? table: ? changed the t adc_s specification (was tbd, is minimum of 383 ns). ? added the footnote ?no missing codes? to the dnl specification. ? added specifications for s nr, thd, sinad, and enob. revised the ?ordering information? section. 23-nov-2010 5 editorial changes and improvements. revised the overview section. replaced references to powerpc with references to power architecture. in the feature summary, changed ?as much as 128 kb on-chip sram? to ?128 kb on-chip sram?. in the ?feature details? section: ? in the ?on-chip sram with ecc? sect ion, added information about required ram wait states. ? in the pit section, deleted ?32-bit counter for real time interrupt, clocked from main external oscillator? (not supported on this device). ? in the flash-memory section, changed ?16 kb test? to ?16 kb test sector?, revised the wait state in formation, and deleted the associated review_q&a content. ? in the sram section, revised the wait state information. in the 100-pin pinout diagram: ? renamed pin 41 (was vdd_hv_adv0_adv1, is vdd_hv_adv). ? renamed pin 42 (was vss_hv_adv0_adv1, is vss_hv_adv). in the 144-pin pinout diagram: ? renamed pin 58 (was vdd_hv_adv0_adv1, is vdd_hv_adv). ? renamed pin 59 (was vss_hv_adv0_adv1, is vss_hv_adv). added the ?lqfp100 pin function summary? table. in the ?lqfp144 pin function summary? table, for pin 39, changed v ss_lv_cor to v dd_lv_cor . in the ?supply pins? table: ? changed the description for v dd_lv_cor (was ?voltage regulator supply voltage?, is ?core logic supply?). ? changed the description for v dd_hv_pmu (was ?core regulator supply?, is ?voltage regulator supply?). in the ?pin muxing? table: ? in the ?pad speed? column headings, changed ?src = 0? to ?src = 1? and ?src = 1? to ?src = 0? ? for port b[6], changed the pad speed for src=0 (was m, is f). in the ?thermal characteristics? sect ion, added meaningful values to the thermal-characteristics tables. added the ?swg electrical specifications? section. in the ?voltage regulator electrical char acteristics? section, changed the table title (was ?hpreg1, hpreg2, main lvds, digital hvd, and digital lvd electrical specifications?, is ?voltage regulator electrical characteristics?) and revised the table. table 44. document revision history (continued) date revision changes
revision history spc56xl60/54 152/160 doc id 15457 rev 8 23-nov-2010 5 (continued) in the ?bcp68 board schematic example? figure, removed the resistor at the base of the bcp68 transistor. in the ?dc electrical characteristics? table: ? changed the guarantee parameter for i inj (was p, is t). ? added a specification for input leaka ge current for shared adc input-only ports. revised the ?flash memory module life? table. in the ?fmpll electrical characteristics? table, revised the footnote defining f scm and f vco . in the ?main oscillator electrical characteristics? table: ? changed the max specification for g mxoschs (was 11.8 ma/v, is 13.25 ma/v). ? revised the conditions for t xoschssu . in the ?rc oscillator electrical characteri stics? table, deleted the specification for rcmtrim . revised the ?adc conversion characteristics? table. in the ?reset pin characteristics? section, changed ?nrstin ? to ?reset ?. added the ?reset sequence? section. revised the footnotes in the ?nexus debug port timing? table. added the mechanical drawing for the 100-pin package. in the ?order codes? table, added a footnote about frequency modulation to the ?speed (mhz)? column heading. 23-mar-2011 6 editorial changes. in the ?document overview? section, added information about how content specific to silicon versions (?cut1? and ?cut2?) is presented. in the isometric miniature package drawings on the front page, removed the third dimension. changed symbol from p to d for ?conversion time? in ?adc conversion characteristics? table. added classification symbol ?d? to seven entries in ?voltage regulator electrical specifications? table. removed irrelevant flexcan specs. updated table ?voltage thresholds? to reference values specified in table ?voltage regulator electrical specifications?. rdy pin added for cut2. in the ?system pins? table, added a footnote about the mdo0 pad speed. updated rsw1 values. added tue-related spec information for single and double adc channels. added ac test timing conditions to the ?ac timing characteristics? section. added a statement on the first page describing cut1 versus cut2. moved the first paragraph from the ?descr iption? section to the beginning of the ?document overview? section. changed pad speed from ?m? to ?sym? for flexray pins in the ?pin muxing? table and added this pad type to the footnote. moved the newly added device current specification entries from the ?dc electrical characteristics? table into a newly created ?supply current characteristics? table. table 44. document revision history (continued) date revision changes
spc56xl60/54 revision history doc id 15457 rev 8 153/160 23-mar-2011 6 (continued) added symbol ?cc? to the descript ion in the ?introduction? section. updated ?input leakage current? specs in the ?dc electrical characteristics? table. changed t adc_s to t sample and t adc_c tot conv in the ?adc conversion characteristics? table and footnotes. removed ?iinj? from the ?adc conversion characteristics? table as this is included in is1wiknj and is1wwinj. changed reset_b to reset in the "reset sequence" section. added the ?flash memory timing? table. added cut2 specs for t drb and t erlb to the ?reset sequences? table. added ?wkup/nmi timing? subsection and ?wkup/nmi glitch filter? table to the ?ac timing characteristics? section. added ?nexus ddr mode output timing? table to the ?nexus timing? section. removed the ?clkout? diagram from the ?external interrupt timing (irq pin)? section as it is not relevant. corrected an error in the irq timing in the ?external interrupt timing? figure. updated the t sdc parameters in the ?dspi timing? table. renamed the ?electromagnetic interference (emi) characteristics? section (is ?electromagnetic interference (emi) c haracteristics (cut1)?) and revised all information in that section. in the ?voltage regulator electrical c haracteristics? section, added the bcx68 from infineon to the list of supported transistors. revised the ?voltage regulator electrical specifications? table to include cut1 and cut2 information. renamed the ?supply current characteristics? section (is ?supply current characteristics (cut2)?) and revised it to show meaningful data. in the footnotes of the ?main oscillator electrical characteristics? table, changed selmargin to xosc_margin. in the ?adc conversion characteristics? table: ? changed ?lsb? to ?counts?. ? created separate rows for the tue specifications. removed the bga row from the ?temperature? table entry. added bullet regarding halt and stop in the ?clock, reset, power, mode and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me)? subsection of the ?features? section. in the ?analog-to-digital converter module? subsection of the ?feature details? section, changed ?motor control mode? to ?ctu mode? to be consistent with the nomenclature used in the reference manual. updated the jcomp entries in the ?pin function summary? table. added footnotes regarding pad pull device s to nmi, tms, tck, and jcomp in the ?system pins? table. added ?time constant of rc filter at lvd input? parameters to the ?main supply lvd (lvd main) specifications? table. table 44. document revision history (continued) date revision changes
revision history spc56xl60/54 154/160 doc id 15457 rev 8 23-mar-2011 6 (continued) in the ?supply current characteristics (cut2)? table: ? changed ?i dd_lv_max ? to ?i dd_lv_max ?; ? removed all ?40-120 mhz? frequency ranges from the ?conditions? column; ? updated the ?max? values column; ? added parameter ?i dd_lv_typ +i dd_lv_pll ? with ?p? classification and special footnote; ? changed all ?25 c? temperature conditions to ?ambient?; ? added ?t j = 150 c? condition to parameters i dd_hv_adc , i dd_hv_aref ., i dd_hv_osc , and i dd_hv_flash . changed the timing diagram in the ?main oscillator electrical characteristics? section to reference mtrans assertion instead of v ddmin . updated the jitter specs in the ?fmpll electrical characteristics? table. in the ?adc conversion characteristics? table, changed all parameters with units of ?counts? to units of ?lsb? and updated min/max values. changed i dd_lv_bist + i dd_lv_pll operating current (for both cases) to tbd. in the ?supply current characteristics (cut2)? section, add ed a footnote that i dd_hv_adc and i dd_hv_aref represent the total current of both adcs in the ?current consumption characteristics? table. in the ?adc conversion characteristics? table: ? changed dnl min from -2 to -1. ? changed ofs min from -2 to -6. ? changed ofs max from 2 to 6. ? changed gne min from -2 to -6. ? changed gne max from 2 to 6. ? changed snr min from 69 to 67. ? changed tue min (without current injection) from -6 to -8. ? changed tue max (without current injection) from 6 to 8. ? changed tue min (with current injection) from -8 to -10. changed tue max (with current injection) from 8 to 10. table 44. document revision history (continued) date revision changes
spc56xl60/54 revision history doc id 15457 rev 8 155/160 14-sep-2011 7 in the ?description? section, changed the first paragraph and its bullets to paragraph form only. in the ?voltage regulator electrical specifications? table, changed the c v1v2 min value from ??? to 300 nf, and changed the max value from 300 nf to 900 nf. in the ?supply current characteristics (cut2)? table, corrected the ?i dd_lv_typ +i dd_lv_pll ? values as follows: ? changed the maximum value for ?t j = ambient? from ?279 ma+ 2.10 ma*f cpu ? to ?279 ma?. ? changed the maximum value for ?t j =150 c? from ?318 ma+ 2.30 ma*f cpu ? to 318 ma. ? changed the frequency multiplier ?f cpu ? in the max value to read ?f cpu [mhz]? for ?i dd_lv_full +i dd_lv_pll ? and ?i dd_lv_typ +i dd_lv_pll ?. in the ?jtag pin ac electrical characteristics? table: ? changed t jcyc min from 100ns to 62.5ns. ? changed t jdc units from ?ns? to ?%?. in the ?nexus debug port timing? table: ? changed t tcyc min from 40ns to 62.5 ns. ? changed t jov parameter description from ?tck low to tdo data valid? to ?tck low to tdo/rdy data valid?. changed ?ddr? to ?double data rate (ddr)? in the ?nexus ddr mode output timing? figure. changed ?tdo? to ?tdo/rdy? in the ?nex us tdi, tms, tdo timing? figure. removed ?f max ? from the ?dspi timing? table. deleted ?order code? table. table 44. document revision history (continued) date revision changes
revision history spc56xl60/54 156/160 doc id 15457 rev 8 01-aug-2012 8 editorial changes. in the ?block diagram? section, removed one pmu from the figure. in the 257-pin pinout figure, changed cut2 to cut2/3 in notes. in the pin function summary table, changed cut2 to cut2/3. in the ?system pins? table: ? added note regarding open drain enable. ? added description to reset pin. in the pin-muxing table: ? added note about open drain. ? changed cut2 to cut2/3. ? changed all entries of column 'weak pull config during reset? to ' - ' , except for pcr[2], pcr[3], pcr[4] and pcr[21]. in the ?absolute maximum ratings? table: ? removed the ?v ss_hv_reg ? row. ? added the footnote ?internal structures hold the input voltage...? to the v in maximum specifications. in the ?recommended operating conditions? table, removed the ?v ss_hv_reg ? row. in the ?thermal characteristics? section: ? added the ?thermal characteristics for lqfp100 package? table. ? updated values and footnote 1 in the 144 package table. ? updated footnote 1 in the 257 package table. in the ?supply current characteristics? table: ? added footnote 1 to parameter ?i dd_lv_typ + i dd_lv_pll ? (symbol ?t?). ? changed ?i dd_lv_stop ? at 150c from 80ma to 72ma. ? changed ?i dd_lv_halt ? at 150c from 72ma to 80ma. in the ?fmpll electrical characteristics? table: ? deleted the footnote ?this value is true when operating at frequencies above 60 mhz...? from the specification for f cs and f ds . ? changed ?f sys ? to ?f fmpllout ? in the entries for the c jitter , f lck , f ul , f cs , and f ds specifications. in the ?adc conversion characteristics? table: ? revised the entry for tue is1winj (was p/t and ?total unadjusted error for is1winj?, is t and ?total unadjusted error for is1winj (single adc channels)?). ? revised the entry for tue is1wwinj (was ?total unadjusted error for is1wwinj?, is ?total unadjusted error for is1wwinj (double adc channels)?). in the ?temperature sensor electrical characteristics? table, for t j = t a to 125 c, changed min/max from values -7/+7 to -10/+10. in the ?input impedance and adc accuracy? section: ? changed c s in the text from 3 pf to 7.5 pf. ? changed r eq in the text from 330 k to 133 k . ?removed r l , r sw , and r ad from the external network design constraint equation and the sentence i mmediately preceding it. ? changed the c f constraint value equation constant from 2048 to 8192. in the ?adc conversion characteristics? table, changed inl min/max values from -2/+2 to -3/+3. table 44. document revision history (continued) date revision changes
spc56xl60/54 revision history doc id 15457 rev 8 157/160 01-aug-2012 8 (cont.) ?in section 1.5.31, ?etimer module ? changed text from ?the mpc5643l provides three etimer modules on the 257 mapbga device, and two etimer modules on the 144 lqfp package? to ?the mpc5643l provides three etimer modules (on the lqfp package etimer_2 is available internally only without any external i/o access)?. ?in section 3.5, ?electromagnetic in terference (emi) characteristics ?,added additional information at the end of this section. ?in section 3.8, voltage regulator electrical characteristics , added text related to external ballast transistor. ?in ta bl e 4 and table 5 (lfbga257 pin function summary) , moved evti from output function to input function. ?in table 7 (system pins) , changed the direction for extal from ?output only? to ?input/output?. ?in ta b l e 7 , added table footnote for symbol ?extal?. ? changed the row (tvdd) in table 9 (absolute maximum ratings) . ?in ta bl e 9 , maximum value for ?v dd_hv_iox ? and ?v dd_hv_fla ? changed from ?3.6? to ?4.0?. ?in table 21 (current consum ption characteristics) , added max value 250 and 290 ma for symbol i dd_lv_bist +i dd_lv_pll . ? added five additional runidd parameters in table 21 (current consumption characteristics) . ?in table 22 (temperature sensor electrical characteristics) , changed condition for parameter ?accuracy? from ?-40c to 25c? to ?-40c to 150c? ?in table 24 (fmpll electrical characteristics) ,added ?150? to the max value for ?f scm ? in table 25 (rc oscillator electrical characteristics) ,changes done are: f rc symbol- added min value ?15.04? and max value ?16.96?.removed condition ?t j =25c? removed row containing rcmvar symbol. ?in figure 9 , added the name ?c s ? to the capacitor in the internal circuit scheme. ? removed references to cut1 and cut2: renamed section ?electromagnetic interfer ence (emi) characteristics (cut1)? to ?electromagnetic interferenc e (emi) characteristics? . in table 26 (adc conversion characteristics) , removed reference to cut2 only for symbol ?is1winj? and ?tue is1wwinj ?. in section 1.1, document overview , modified text to remove references to ?cut1?. ?in table 26 (adc conversion characteristics) , for t conv added ?60 mhz? to ?conditions? and ?600? to the ?min? value. separated snr into two specifications with conditions vref 3.3 v and 5.0 v respectively. table 44. document revision history (continued) date revision changes
revision history spc56xl60/54 158/160 doc id 15457 rev 8 01-aug-2012 8 (cont.) changed min value to ?-72? for symbol ?thd?. ?in table 26 (adc conversion characteristics) , changed adc specification parameter ?thd? minimum limit from -72 to -65db. ?in table 27 (flash memory program and erase electrical specifications) , changes done are as follows: t dwprogram , changed typical value from ?39? to ?38?. t pprogram , changed typical value from ?48? to ?45? and intial max value from ?100? to ?160?. t 16kpperase , inserted typical value ?270? and factory avg ?1000?. t 48kpperase , inserted typical value ?625? and factory avg ?1500?. t 64kpperase , inserted typical value ?800? and factory avg ?1800?. t 128kpperase , inserted typical value ?1500? and factory avg ?2600?. t 256kpperase , inserted typical value ?3000? and factory avg ?5200?. updated table footnote and removed min column in table 27 (flash memory program and erase electrical specifications) ?in table 28 (flash memory timing) , added symbol t psrt ,t esrt and added table footnote for t psrt ,t esrt . ? added table 30 (mpc5643l swg specifications) ?in table 30 (mpc5643l swg specifications) added table footnote for common mode. changed text from ?internal device pad resistance? to ?internal device routing resistance?. ? added figure 27 in section 3.20.4, ?nexus timing ?. ?in table 31 (pad ac specifications (3.3 v , ipp_hve = 0 )) , removed the row of pad ?pull up/downc(3.6 v max)?. ?in figure 43 , updated part numbers (changed ?ppc? to ?spc? and ?f0? to ?f2?). ?replaced figure 41 , figure 42 with the new versions. ?in table 19 (voltage regulator electrical specifications) ,changed the symbol of spec external decoupling capacitor from sr to c ext . in figure 5 , changed the esr range in note text to 1 mw to 100 mw from 30 mw to 150 mw. ?in section 1.5.32, ?sine wave generator (swg) ? removed the following text: frequency range from 1khz to 50khz. sine wave amplitude from 0.47 v to 2.26 v. ?in table 21 (current consumption characteristics) ,changed symbol from ?c? to ?t? , added ?operating current? to the parameter and updated the maximum value for five additional runidd parameters. ?in table 21 (current consumption characteristics) , changed ?conditions? from ?1.2 v supplies? to ?1.2 v supplies during lbist (full lbist configuration)? for all the parameters. removed table ?swg electrical characteristics?. table 44. document revision history (continued) date revision changes
spc56xl60/54 revision history doc id 15457 rev 8 159/160 01-aug-2012 8 (cont.) ?in table 19 (voltage regulator electrical specifications) , changed the ?digital supply high voltage detector upper threshold low limit (after a destructive reset initialization phase completion)? from 1.43v to 1.38v. ? added table 18 (recommended operating characteristics) . ? updated the idd values in table 21 (current consumption characteristics) . changed conditions text from ?1.2 supplies during lbist (full lbist configuration)? to ?1.2 v supplies? for all the idd parameters except i dd_lv_bist +i dd_lv_pll . added footnote in ?conditions? for the dpm mode. ? removed cut references from the whole document. in table 26 (adc conversion characteristics) , changed the sampling frequency value from ?1 mhz? to ?983.6 khz?. table 44. document revision history (continued) date revision changes
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